[Intel-gfx] [PATCH] drm/i915/gt: WaSetVfGuardbandPreemptionVertexCount (bdw/chv)

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-07-22 16:55:39)
> 
> 
> On 22/07/2019 14:18, Chris Wilson wrote:
> > As a w/a for data corruption, we are told to set the preemption vertex
> > count to 0x20 on boot. As it is a counter, once contexts are active we
> > do not expect the value to be retained, so hide it from the wa-list
> > verification.
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +++++++++++++++++++++
> >   1 file changed, 24 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 704ace01e7f5..7628f8463317 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -647,6 +647,26 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
> >       return 0;
> >   }
> >   
> > +static void
> > +gen8_gt_workarounds_init(struct drm_i915_private *i915,
> > +                      struct i915_wa_list *wal)
> > +{
> > +     /* WaSetVfGuardbandPreemptionVertexCount:bdw,chv */
> > +     wa_write_masked_or(wal, _MMIO(0x83A4), 0, 0xffff0020);
> 
> 0x83a4 is listed in saved state for the context so have you tried 
> putting it as a context workaround?

It explicitly said at boot, so it made me think it has to be before we
even load a context / wake up the gpu. How on earth a counter value leads
to corruption I have no idea, nor what is so special about 32. Nor why a
counter would be masked.
-Chris