[Intel-gfx] [PATCH 21/22] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers

[Lucas De Marchi]

On Mon, Jul 22, 2019 at 01:11:40PM +0530, Anshuman Gupta wrote:
>On 2019-07-19 at 11:39:54 -0700, Lucas De Marchi wrote:
>> On Thu, Jul 18, 2019 at 11:17:03AM +0530, Anshuman Gupta wrote:
>> >On 2019-07-12 at 18:09:39 -0700, Lucas De Marchi wrote:
>> >>From: José Roberto de Souza <jose.souza at intel.com>
>> >>
>> >>Tiger Lask has a new register offset for DC5 and DC6 residency counters.
>> >>
>> >>Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
>> >>Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
>> >>---
>> >> drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++--------
>> >> drivers/gpu/drm/i915/i915_reg.h     |  2 ++
>> >> 2 files changed, 15 insertions(+), 8 deletions(-)
>> >>
>> >>diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> >>index a1843e3de6d7..4b12b5588dd6 100644
>> >>--- a/drivers/gpu/drm/i915/i915_debugfs.c
>> >>+++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> >>@@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>> >> 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>> >> 	intel_wakeref_t wakeref;
>> >> 	struct intel_csr *csr;
>> >>+	i915_reg_t dc5_reg, dc6_reg = {};
>> >>
>> >> 	if (!HAS_CSR(dev_priv))
>> >> 		return -ENODEV;
>> >>@@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>> >> 	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
>> >> 		   CSR_VERSION_MINOR(csr->version));
>> >>
>> >>-	if (WARN_ON(INTEL_GEN(dev_priv) > 11))
>> >>-		goto out;
>> >>+	if (INTEL_GEN(dev_priv) >= 12) {
>Below DMC debug registers offsets are specific to TGL,
>So it would make sense to add IS_TIGERLAKE condition?

I think we can leave it with gen >= 12 and change it when/if the next
platform change that.


>> >>+		dc5_reg = TGL_CSR_DC5_RES_COUNT;
>> >>+		dc6_reg = TGL_CSR_DC6_RES_COUNT;
>> >>+	} else {
>> >>+		dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
>> >>+						 SKL_CSR_DC3_DC5_COUNT;
>> >>+		if (!IS_GEN9_LP(dev_priv))
>> >>+			dc6_reg = SKL_CSR_DC5_DC6_COUNT;
>> >>+	}
>> >>
>> >>-	seq_printf(m, "DC3 -> DC5 count: %d\n",
>> >>-		   I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
>> >>-						    SKL_CSR_DC3_DC5_COUNT));
>> >>-	if (!IS_GEN9_LP(dev_priv))
>> >>-		seq_printf(m, "DC5 -> DC6 count: %d\n",
>> >>-			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
>> >>+	seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
>> >>+	if (dc6_reg.reg)
>> >>+		seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
>> >>
>> >> out:
>> >> 	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
>> >>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> >>index 6cfcdf6bb1bb..5e3434cdd1e8 100644
>> >>--- a/drivers/gpu/drm/i915/i915_reg.h
>> >>+++ b/drivers/gpu/drm/i915/i915_reg.h
>> >>@@ -7269,6 +7269,8 @@ enum {
>> >> #define SKL_CSR_DC3_DC5_COUNT	_MMIO(0x80030)
>> >> #define SKL_CSR_DC5_DC6_COUNT	_MMIO(0x8002C)
>> >> #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
>> >>+#define TGL_CSR_DC5_RES_COUNT	_MMIO(0x101084)
>> >>+#define TGL_CSR_DC6_RES_COUNT	_MMIO(0x101088)
>> >CSR memory ranges from 0x80000 till 0x8ffff
>> >These DMC_DEBUG regisers are not are not CSR register.
>> >It would make sense to rename the macro.
>>
>> True.
>>
>> TGL_DMC_DEBUG_DC5_COUNT and TGL_DMC_DEBUG_DC6_COUNT sounds good?
>yes!

thanks, I'll send an updated version.

Lucas De Marchi

>>
>> Lucas De Marchi
>>
>> >>
>> >> /* interrupts */
>> >> #define DE_MASTER_IRQ_CONTROL   (1 << 31)
>> >>--
>> >>2.21.0
>> >>
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