[Intel-gfx] [PATCH 01/23] drm/i915: Move aliasing_ppgtt underneath its i915_ggtt

[Tvrtko Ursulin]

On 24/07/2019 10:47, Chris Wilson wrote:
> Quoting Chris Wilson (2019-07-24 10:37:19)
>> Quoting Chris Wilson (2019-07-24 10:27:38)
>>> Quoting Tvrtko Ursulin (2019-07-24 09:56:34)
>>>>
>>>> On 23/07/2019 19:38, Chris Wilson wrote:
>>>>> +static int __context_pin_ppgtt(struct intel_context *ce)
>>>>>    {
>>>>>        struct i915_address_space *vm;
>>>>>        int err = 0;
>>>>>    
>>>>> -     vm = ctx->vm ?: &ctx->i915->mm.aliasing_ppgtt->vm;
>>>>> +     vm = vm_alias(ce);
>>>>>        if (vm)
>>>>
>>>> Can't return NULL it seems. (Same below.)
>>>
>>> Are you so sure?
>>>
>>> ce->gem_context->vm is only !NULL if there is a full-ppgtt
>>> &ggtt->alias->vm is only !NULL if there is an aliasing-ppgtt
>>>
>>> There may be contexts with neither (gen4, gen5).
>>
>> It's not until the next patch where we always set ce->vm will it be
>> non-NULL. Point taken.
> 
> Except, we purposely replace the i915_ggtt ce->vm with its alias, which
> may still be NULL. (Which is fine as that is perma-pinned and we don't
> need to fiddle.)

I saw address of and though "it can't be NULL", but forgot about tricks 
with member at offset zero.. nvm.. Drop a comment if you feel like it. 
At least it is now consolidated so there is a place.

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Regards,

Tvrtko