[Intel-gfx] [PATCH v12 1/2] drm: Introduce new DRM_FORMAT_XYUV

[Matt Roper]

On Tue, Nov 20, 2018 at 04:27:21PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 09, 2018 at 11:39:15AM +0200, Stanislav Lisovskiy wrote:
> > v5: This is YUV444 packed format same as AYUV, but without alpha,
> >     as supported by i915.
> > 
> > v6: Removed unneeded initializer for new XYUV format.
> > 
> > v7: Added is_yuv field initialization according to latest
> >     drm_fourcc format structure initialization changes.
> > 
> > v8: Edited commit message to be more clear about skl+, renamed
> >     PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
> >     doesn't support per-pixel alpha. Fixed minor code issues.
> > 
> > v9: Moved DRM format check to proper place in intel_framebuffer_init.
> > 
> > v10: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888
> > 
> > v11: Fixed rebase conflict, caused by added new formats to drm-tip
> >      meanwhile.
> > 
> > Reviewed-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe at arm.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> 
> Pushed this one to drm-misc-next. Thanks for the patch and review.
> 
> The i915 part won't apply properly in drm-misc-next, so we'll need
> to wait until dinq and drm-misc-next are suitably aligned before
> we push that one.

It looks like we forgot to ever go back and apply the i915 patch here.
Any plans to rebase/report it so we can get it landed?


Matt

> 
> > ---
> >  drivers/gpu/drm/drm_fourcc.c  | 1 +
> >  include/uapi/drm/drm_fourcc.h | 1 +
> >  2 files changed, 2 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> > index f523948c82b1..94d358eb0b8d 100644
> > --- a/drivers/gpu/drm/drm_fourcc.c
> > +++ b/drivers/gpu/drm/drm_fourcc.c
> > @@ -237,6 +237,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
> >  		{ .format = DRM_FORMAT_X0L2,		.depth = 0,  .num_planes = 1,
> >  		  .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },
> >  		  .hsub = 2, .vsub = 2, .is_yuv = true },
> > +		{ .format = DRM_FORMAT_XYUV8888,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> >  	};
> >  
> >  	unsigned int i;
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index e7e48f1f4a74..0b44260a5ee9 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -151,6 +151,7 @@ extern "C" {
> >  #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
> >  
> >  #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
> > +#define DRM_FORMAT_XYUV8888		fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
> >  
> >  /*
> >   * packed YCbCr420 2x2 tiled formats
> > -- 
> > 2.17.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel
> _______________________________________________
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> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795