[Intel-gfx] [PATCH v3 3/9] drm/i915/tgl: Add power well to enable DC3CO state

[Anshuman Gupta]

"DC3CO Off" power well inherits its power domains from
"DC Off" power well, these power domains will disallow
DC3CO when any external displays are connected and at
time of modeset and aux programming.
Renaming "DC Off" power well to "DC5 Off" power well.

v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
    Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
    Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
    to a appropriate place haswell_crtc_enable(). [Imre]
    Changed the DC3CO power well enabled call back logic as
    recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]

Cc: Nikula, Jani <jani.nikula at intel.com>
Cc: Deak, Imre <imre.deak at intel.com>
Cc: Manna, Animesh <animesh.manna at intel.com>
Cc: Vivi, Rodrigo <rodrigo.vivi at intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 72 ++++++++++++++++++-
 1 file changed, 71 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index d9585d08e081..1d2aced7f0e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -791,6 +791,30 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
 	dev_priv->csr.dc_state = val & mask;
 }
 
+static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
+{
+	gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+
+	val = I915_READ(DC_STATE_EN);
+	val &= ~DC_STATE_DC3CO_STATUS;
+	I915_WRITE(DC_STATE_EN, val);
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+	/*
+	 * Delay of 200us DC3CO Exit time B.Spec 49196
+	 * Every time it is not necessary that DC3CO exit will completed,
+	 * when we disallow DC3CO.
+	 * It might not have got chance to enter DC3CO earlier.
+	 */
+	if (wait_for_us(I915_READ(DC_STATE_EN) &
+				    DC_STATE_DC3CO_STATUS, 200))
+		DRM_INFO("Timed out waiting for dc3co exit\n");
+}
+
 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 {
 	assert_can_enable_dc9(dev_priv);
@@ -1007,6 +1031,33 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 		gen9_enable_dc5(dev_priv);
 }
 
+static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv,
+					struct i915_power_well *power_well)
+{
+	tgl_disallow_dc3co(dev_priv);
+}
+
+static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv,
+					 struct i915_power_well *power_well)
+{
+	if (WARN_ON(!dev_priv->psr.sink_psr2_support))
+		return;
+
+	if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+		tgl_allow_dc3co(dev_priv);
+}
+
+static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
+					 struct i915_power_well *power_well)
+{
+	/*
+	 * Checking alone DC_STATE_EN is not enough as DC5 power well also
+	 * allow/disallow DC3CO to make sure both are not enabled at same time
+	 */
+	return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+		(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
+}
+
 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
 					 struct i915_power_well *power_well)
 {
@@ -2611,6 +2662,12 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) |	\
 	BIT_ULL(POWER_DOMAIN_INIT))
 
+#define TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS (		\
+	TGL_PW_2_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_MODESET) |			\
+	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
 #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
 	TGL_PW_2_POWER_DOMAINS |			\
 	BIT_ULL(POWER_DOMAIN_MODESET) |			\
@@ -2715,6 +2772,13 @@ static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
 	.is_enabled = gen9_dc_off_power_well_enabled,
 };
 
+static const struct i915_power_well_ops tgl_dc3co_power_well_ops = {
+	.sync_hw = i9xx_power_well_sync_hw_noop,
+	.enable = tgl_dc3co_power_well_enable,
+	.disable = tgl_dc3co_power_well_disable,
+	.is_enabled = tgl_dc3co_power_well_enabled,
+};
+
 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
 	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = bxt_dpio_cmn_power_well_enable,
@@ -3626,11 +3690,17 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 		},
 	},
 	{
-		.name = "DC off",
+		.name = "DC5 off",
 		.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
 		.ops = &gen9_dc_off_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 	},
+	{
+		.name = "DC3CO off",
+		.domains = TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS,
+		.ops = &tgl_dc3co_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+	},
 	{
 		.name = "power well 2",
 		.domains = TGL_PW_2_POWER_DOMAINS,
-- 
2.21.0