[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915 vgpu PV to improve vgpu performance
Patchwork
patchwork at emeril.freedesktop.org
Mon Jun 3 07:23:57 UTC 2019
== Series Details ==
Series: i915 vgpu PV to improve vgpu performance
URL : https://patchwork.freedesktop.org/series/61493/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b84d8b472a53 drm/i915: introduced vgpu pv capability
-:90: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#90: FILE: drivers/gpu/drm/i915/i915_vgpu.c:89:
+ DRM_INFO("Virtual GPU for Intel GVT-g detected with pv_caps 0x%x.\n",
+ dev_priv->vgpu.pv_caps);
total: 0 errors, 0 warnings, 1 checks, 99 lines checked
8f6296420e40 drm/i915: vgpu shared memory setup for pv optimization
-:113: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#113: FILE: drivers/gpu/drm/i915/i915_vgpu.c:318:
+ __raw_uncore_write32(uncore, vgtif_reg(g2v_notify),
+ VGT_G2V_SHARED_PAGE_SETUP);
total: 0 errors, 0 warnings, 1 checks, 132 lines checked
61bce586be7a drm/i915: vgpu ppgtt update pv optimization
-:41: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line
#41: FILE: drivers/gpu/drm/i915/i915_gem.c:1511:
+ if ((intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
+ || intel_vgpu_enabled_pv_caps(dev_priv, PV_PPGTT_UPDATE))
-:55: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#55: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:930:
+void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
u64 start, u64 length)
-:64: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#64: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:1169:
+void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
struct i915_vma *vma,
-:73: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#73: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:1451:
+int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
u64 start, u64 length)
-:95: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#95: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:650:
+void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
+ u64 start, u64 length);
-:97: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#97: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:652:
+void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
+ struct i915_vma *vma,
-:100: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#100: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:655:
+int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
+ u64 start, u64 length);
-:138: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#138: FILE: drivers/gpu/drm/i915/i915_vgpu.c:296:
+static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm,
+ u64 start, u64 length)
-:157: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#157: FILE: drivers/gpu/drm/i915/i915_vgpu.c:315:
+static void gen8_ppgtt_insert_4lvl_pv(struct i915_address_space *vm,
+ struct i915_vma *vma,
-:176: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#176: FILE: drivers/gpu/drm/i915/i915_vgpu.c:334:
+static int gen8_ppgtt_alloc_4lvl_pv(struct i915_address_space *vm,
+ u64 start, u64 length)
-:203: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#203: FILE: drivers/gpu/drm/i915/i915_vgpu.c:361:
+void intel_vgpu_config_pv_caps(struct drm_i915_private *dev_priv,
+ enum pv_caps cap, void *data)
-:245: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#245: FILE: drivers/gpu/drm/i915/i915_vgpu.h:91:
+intel_vgpu_enabled_pv_caps(struct drm_i915_private *dev_priv,
+ enum pv_caps cap)
-:248: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line
#248: FILE: drivers/gpu/drm/i915/i915_vgpu.h:94:
+ return intel_vgpu_active(dev_priv) && intel_vgpu_has_pv_caps(dev_priv)
+ && (dev_priv->vgpu.pv_caps & cap);
-:257: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#257: FILE: drivers/gpu/drm/i915/i915_vgpu.h:103:
+void intel_vgpu_config_pv_caps(struct drm_i915_private *dev_priv,
+ enum pv_caps cap, void *data);
total: 0 errors, 0 warnings, 14 checks, 193 lines checked
f1b3f498ebea drm/i915: vgpu context submission pv optimization
-:132: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#132:
new file mode 100644
-:152: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#152: FILE: drivers/gpu/drm/i915/intel_pv_submission.c:16:
+ reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
^
total: 0 errors, 1 warnings, 1 checks, 237 lines checked
40ce001e1ce8 drm/i915/gvt: GVTg handle pv_caps PVINFO register
4becca4775d1 drm/i915/gvt: GVTg handle shared_page setup
-:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#50: FILE: drivers/gpu/drm/i915/gvt/gvt.h:693:
+int intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+ unsigned int offset, void *buf, unsigned long len);
-:52: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#52: FILE: drivers/gpu/drm/i915/gvt/gvt.h:695:
+int intel_gvt_write_shared_page(struct intel_vgpu *vgpu,
+ unsigned int offset, void *buf, unsigned long len);
-:130: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#130: FILE: drivers/gpu/drm/i915/gvt/vgpu.c:603:
+int intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+ unsigned int offset, void *buf, unsigned long len)
-:149: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#149: FILE: drivers/gpu/drm/i915/gvt/vgpu.c:622:
+int intel_gvt_write_shared_page(struct intel_vgpu *vgpu,
+ unsigned int offset, void *buf, unsigned long len)
total: 0 errors, 0 warnings, 4 checks, 122 lines checked
3626e6547796 drm/i915/gvt: GVTg support ppgtt pv optimization
-:82: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#82: FILE: drivers/gpu/drm/i915/gvt/gtt.c:1826:
+ gvt_vgpu_err("fail to create ppgtt for pdp 0x%llx\n",
+ px_dma(&mm->ppgtt->pml4));
-:112: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#112: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2858:
+int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[])
-:137: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#137: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2883:
+int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[])
-:165: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects?
#165: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2911:
+#define pml4_addr_end(addr, end) \
+({ unsigned long __boundary = \
+ ((addr) + GEN8_PML4E_SIZE) & GEN8_PML4E_SIZE_MASK; \
+ (__boundary < (end)) ? __boundary : (end); \
+})
-:171: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects?
#171: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2917:
+#define pdp_addr_end(addr, end) \
+({ unsigned long __boundary = \
+ ((addr) + GEN8_PDPE_SIZE) & GEN8_PDPE_SIZE_MASK; \
+ (__boundary < (end)) ? __boundary : (end); \
+})
-:177: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects?
#177: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2923:
+#define pd_addr_end(addr, end) \
+({ unsigned long __boundary = \
+ ((addr) + GEN8_PDE_SIZE) & GEN8_PDE_SIZE_MASK; \
+ (__boundary < (end)) ? __boundary : (end); \
+})
-:190: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#190: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2936:
+static int walk_pt_range(struct intel_vgpu *vgpu, u64 pt,
+ u64 start, u64 end, struct ppgtt_walk *walk)
-:203: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#203: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2949:
+ ret = intel_gvt_hypervisor_read_gpa(vgpu,
+ (pt & PAGE_MASK) + (start_index << info->gtt_entry_size_shift),
-:224: CHECK:LINE_SPACING: Please don't use multiple blank lines
#224: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2970:
+
+
-:226: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#226: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2972:
+static int walk_pd_range(struct intel_vgpu *vgpu, u64 pd,
+ u64 start, u64 end, struct ppgtt_walk *walk)
-:238: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#238: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2984:
+ ret = intel_gvt_hypervisor_read_gpa(vgpu,
+ (pd & PAGE_MASK) + (index <<
-:251: CHECK:LINE_SPACING: Please don't use multiple blank lines
#251: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2997:
+
+
-:253: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#253: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2999:
+static int walk_pdp_range(struct intel_vgpu *vgpu, u64 pdp,
+ u64 start, u64 end, struct ppgtt_walk *walk)
-:265: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#265: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3011:
+ ret = intel_gvt_hypervisor_read_gpa(vgpu,
+ (pdp & PAGE_MASK) + (index <<
-:277: CHECK:LINE_SPACING: Please don't use multiple blank lines
#277: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3023:
+
+
-:279: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#279: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3025:
+static int walk_pml4_range(struct intel_vgpu *vgpu, u64 pml4,
+ u64 start, u64 end, struct ppgtt_walk *walk)
-:290: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#290: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3036:
+ ret = intel_gvt_hypervisor_read_gpa(vgpu,
+ (pml4 & PAGE_MASK) + (index <<
-:303: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#303: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3049:
+int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[])
-:337: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#337: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3083:
+ walk.mfns = kmalloc_array(num_pages,
+ sizeof(unsigned long), GFP_KERNEL);
-:397: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#397: FILE: drivers/gpu/drm/i915/gvt/gtt.h:282:
+int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[]);
-:400: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#400: FILE: drivers/gpu/drm/i915/gvt/gtt.h:285:
+int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[]);
-:403: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#403: FILE: drivers/gpu/drm/i915/gvt/gtt.h:288:
+int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[]);
-:413: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'vgpu' - possible side-effects?
#413: FILE: drivers/gpu/drm/i915/gvt/gvt.h:56:
+#define VGPU_PVCAP(vgpu, cap) \
+ ((vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) & (cap)) \
+ && vgpu->shared_page_enabled)
-:415: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line
#415: FILE: drivers/gpu/drm/i915/gvt/gvt.h:58:
+ ((vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) & (cap)) \
+ && vgpu->shared_page_enabled)
total: 0 errors, 0 warnings, 24 checks, 412 lines checked
fa6226cbb013 drm/i915/gvt: GVTg support context submission pv optimization
-:70: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#70: FILE: drivers/gpu/drm/i915/gvt/handlers.c:1708:
+ if (intel_gvt_read_shared_page(vgpu, pv_elsp_off,
+ &execlist->elsp_dwords.data, sizeof(struct pv_submission)))
total: 0 errors, 0 warnings, 1 checks, 67 lines checked
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