[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/10] drm/i915: Add windowing for primary planes on gen2/3 and chv

[Ville Syrjälä]

On Fri, May 31, 2019 at 04:05:51PM +0300, Ville Syrjälä wrote:
> On Thu, May 30, 2019 at 05:43:00AM -0000, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: series starting with [01/10] drm/i915: Add windowing for primary planes on gen2/3 and chv
> > URL   : https://patchwork.freedesktop.org/series/61345/
> > State : failure
> > 
> > == Summary ==
> > 
> > CI Bug Log - changes from CI_DRM_6165_full -> Patchwork_13133_full
> > ====================================================
> > 
> > Summary
> > -------
> > 
> >   **FAILURE**
> > 
> >   Serious unknown changes coming with Patchwork_13133_full absolutely need to be
> >   verified manually.
> >   
> >   If you think the reported changes have nothing to do with the changes
> >   introduced in Patchwork_13133_full, please notify your bug team to allow them
> >   to document this new failure mode, which will reduce false positives in CI.
> > 
> >   
> > 
> > Possible new issues
> > -------------------
> > 
> >   Here are the unknown changes that may have been introduced in Patchwork_13133_full:
> > 
> > ### IGT changes ###
> > 
> > #### Possible regressions ####
> > 
> >   * igt at kms_plane@pixel-format-pipe-a-planes:
> >     - shard-glk:          [PASS][1] -> [FAIL][2]
> >    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-glk3/igt@kms_plane@pixel-format-pipe-a-planes.html
> >    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-glk8/igt@kms_plane@pixel-format-pipe-a-planes.html
> 
> <7> [125.370679] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
> ...
> <7> [125.542650] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz, bypass 19200 kHz, voltage
> level 4
> ...
> <7> [133.682144] [drm:skl_check_pipe_max_pixel_rate [i915]] Max supported pixel clock with scaling exceeded
> 
> Max pixel rate for 64bpp is 79.2*2 * 8/9 = 140.8 Mhz, which we are
> exceeding. We'd need some way to bump the cdclk for this case, but
> the kernel will only do that for modesets, and it won't account for
> that 8/9 factor. Not sure there is a great way to handle these sorts
> of cases.
> 
> > 
> >   * igt at kms_plane_scaling@pipe-c-scaler-with-pixel-format:
> >     - shard-apl:          [PASS][3] -> [FAIL][4] +4 similar issues
> >    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-apl5/igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format.html
> >    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-apl7/igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format.html
> 
> <7> [1749.831610] [drm:drm_atomic_helper_check_plane_state] Invalid scaling of plane
> <7> [1749.831620] [drm:drm_rect_debug_print] src: 8.000000x8.000000+0.000000+0.000000
> <7> [1749.831625] [drm:drm_rect_debug_print] dst: 1920x1080+0+0
> 
> Not quite sure what's going on here. Unfortunately the debugs don't have
> enough information to see what's going on.

Doh. That's obviously the "no scaling with fp16" hardware limitation
kicking in. I'll need to adjust the test somehow to make it skip fp16
on these platforms.

-- 
Ville Syrjälä
Intel