[Intel-gfx] [PATCH] drm/i915/ehl: Add support for DPLL4 (v5)
Imre Deak
imre.deak at intel.com
Thu Jun 6 09:22:53 UTC 2019
On Wed, Jun 05, 2019 at 11:41:28AM -0700, Vivek Kasireddy wrote:
> This patch adds support for DPLL4 on EHL that include the
> following restrictions:
>
> - DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
> DPLL4 can be used with other DDIs, including DDID
> (combo port A external usage).
>
> - DPLL4 cannot be enabled when DC5 or DC6 are enabled.
>
> - The DPLL4 enable, lock, power enabled, and power state are connected
> to the MGPLL1_ENABLE register.
>
> v2: (suggestions from Bob Paauwe)
> - Rework ehl_get_dpll() function to call intel_find_shared_dpll() and
> iterate twice: once for Combo plls and once for MG plls.
>
> - Use MG pll funcs for DPLL4 instead of creating new ones and modify
> mg_pll_enable to include the restrictions for EHL.
>
> v3: Fix compilation error
>
> v4: (suggestions from Lucas and Ville)
> - Treat DPLL4 as a combo phy PLL and not as MG PLL
> - Disable DC states when this DPLL is being enabled
> - Reuse icl_get_dpll instead of creating a separate one for EHL
>
> v5: (suggestion from Ville)
> - Refcount the DC OFF power domains during the enabling and disabling
> of this DPLL.
>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: José Roberto de Souza <jose.souza at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Vivek Kasireddy <vivek.kasireddy at intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 40 ++++++++++++++++++++++---
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 5 ++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 21 +++++++++++++
> drivers/gpu/drm/i915/intel_runtime_pm.h | 5 ++++
> 4 files changed, 67 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 897d93537414..6d89d231b33d 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -22,8 +22,8 @@
> */
>
> #include "intel_dpio_phy.h"
> -#include "intel_dpll_mgr.h"
> #include "intel_drv.h"
> +#include "intel_dpll_mgr.h"
>
> /**
> * DOC: Display PLLs
> @@ -2806,6 +2806,12 @@ icl_get_dpll(struct intel_crtc_state *crtc_state,
> if (intel_port_is_combophy(dev_priv, port)) {
> min = DPLL_ID_ICL_DPLL0;
> max = DPLL_ID_ICL_DPLL1;
> +
> + if (IS_ELKHARTLAKE(dev_priv)) {
> + if (encoder->type != INTEL_OUTPUT_EDP)
> + max = DPLL_ID_EHL_DPLL4;
> + }
> +
> ret = icl_calc_dpll_state(crtc_state, encoder);
> } else if (intel_port_is_tc(dev_priv, port)) {
> if (encoder->type == INTEL_OUTPUT_DP_MST) {
> @@ -2945,8 +2951,14 @@ static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll,
> struct intel_dpll_hw_state *hw_state)
> {
> - return icl_pll_get_hw_state(dev_priv, pll, hw_state,
> - CNL_DPLL_ENABLE(pll->info->id));
> + i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> +
> + if (IS_ELKHARTLAKE(dev_priv) &&
> + pll->info->id == DPLL_ID_EHL_DPLL4) {
> + enable_reg = MG_PLL_ENABLE(0);
> + }
> +
> + return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
> }
>
> static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
> @@ -3057,6 +3069,14 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
> {
> i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
>
> + if (IS_ELKHARTLAKE(dev_priv) &&
> + pll->info->id == DPLL_ID_EHL_DPLL4) {
> + enable_reg = MG_PLL_ENABLE(0);
> +
> + /* Need to disable DC states when this DPLL is enabled. */
> + icl_disable_dc_states(dev_priv, pll);
> + }
> +
> icl_pll_power_enable(dev_priv, pll, enable_reg);
>
> icl_dpll_write(dev_priv, pll);
> @@ -3152,7 +3172,18 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
> static void combo_pll_disable(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> - icl_pll_disable(dev_priv, pll, CNL_DPLL_ENABLE(pll->info->id));
> + i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> +
> + if (IS_ELKHARTLAKE(dev_priv) &&
> + pll->info->id == DPLL_ID_EHL_DPLL4) {
> + enable_reg = MG_PLL_ENABLE(0);
> + icl_pll_disable(dev_priv, pll, enable_reg);
> +
> + icl_enable_dc_states(dev_priv, pll);
> + return;
> + }
> +
> + icl_pll_disable(dev_priv, pll, enable_reg);
> }
>
> static void tbt_pll_disable(struct drm_i915_private *dev_priv,
> @@ -3230,6 +3261,7 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
> static const struct dpll_info ehl_plls[] = {
> { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
> { },
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index 8835dd20f1d2..5a70134f539f 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -117,6 +117,10 @@ enum intel_dpll_id {
> * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
> */
> DPLL_ID_ICL_DPLL1 = 1,
> + /**
> + * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
> + */
> + DPLL_ID_EHL_DPLL4 = 2,
> /**
> * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
> */
> @@ -312,6 +316,7 @@ struct intel_shared_dpll {
> * @info: platform specific info
> */
> const struct dpll_info *info;
> + intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
> };
>
> #define SKL_DPLL0 0
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 12f5b669f20e..09eb5a5e32fa 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -5229,3 +5229,24 @@ void intel_runtime_pm_init_early(struct drm_i915_private *i915)
> {
> init_intel_runtime_pm_wakeref(i915);
> }
> +
> +void icl_disable_dc_states(struct drm_i915_private *dev_priv,
> + struct intel_shared_dpll *pll)
> +{
> + enum intel_display_power_domain domain;
> +
> + for_each_power_domain(domain, ICL_DISPLAY_DC_OFF_POWER_DOMAINS)
> + pll->wakerefs[domain] = intel_display_power_get(dev_priv,
> + domain);
> +}
Well, using power domains ment adding a new domain for this purpose.
> +
> +void icl_enable_dc_states(struct drm_i915_private *dev_priv,
> + struct intel_shared_dpll *pll)
> +{
> + enum intel_display_power_domain domain;
> +
> + for_each_power_domain(domain, ICL_DISPLAY_DC_OFF_POWER_DOMAINS)
> + intel_display_power_put(dev_priv, domain,
> + pll->wakerefs[domain]);
> +}
> +
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h b/drivers/gpu/drm/i915/intel_runtime_pm.h
> index 0a4c4b3aee7d..a2e8c6799b0a 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.h
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.h
> @@ -139,4 +139,9 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
> bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> enum dpio_channel ch, bool override);
>
> +void icl_disable_dc_states(struct drm_i915_private *dev_priv,
> + struct intel_shared_dpll *pll);
> +void icl_enable_dc_states(struct drm_i915_private *dev_priv,
> + struct intel_shared_dpll *pll);
> +
> #endif /* __INTEL_RUNTIME_PM_H__ */
> --
> 2.21.0
>
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