[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/5] drm/i915: Reset only affected engines when handling error capture (rev3)
URL   : https://patchwork.freedesktop.org/series/61758/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
0bcf26ea6446 drm/i915: Reset only affected engines when handling error capture
07ef2aa03eb8 drm/i915: Tidy engine mask types in hangcheck
8a1a473386ac drm/i915: Make Gen6/7 RING_FAULT_REG access engine centric
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:71:
+#define GEN6_RING_FAULT_REG_READ(engine__) \
+	intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))

-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#27: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:74:
+#define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
+	intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))

-:30: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#30: FILE: drivers/gpu/drm/i915/gt/intel_engine.h:77:
+#define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
+({ \
+	u32 __val; \
+\
+	__val = intel_uncore_read((engine__)->uncore, \
+				  RING_FAULT_REG(engine__)); \
+	__val &= ~(clear__); \
+	__val |= (set__); \
+	intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
+			   __val); \
+})

total: 0 errors, 0 warnings, 3 checks, 52 lines checked
4f51349b0547 drm/i915: Extract engine fault reset to a helper
5b834e860f03 drm/i915: Unexport i915_gem_init/fini_aliasing_ppgtt