[Intel-gfx] [CI 6/6] drm/i915: Remove I915_READ64 and I915_READ64_32x2

[Tvrtko Ursulin]

On 11/06/2019 18:11, Ville Syrjälä wrote:
> On Mon, Jun 10, 2019 at 01:06:08PM +0100, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>>
>> Now that all their users are gone we can remove the macros and
>> accompanying duplicated comment.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>> Suggested-by: Jani Nikula <jani.nikula at intel.com>
>> Reviewed-by: Jani Nikula <jani.nikula at intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h | 18 ------------------
>>   1 file changed, 18 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 20eb37b760c4..d3c02e009a98 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2851,24 +2851,6 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
>>   #define I915_READ_NOTRACE(reg__)	 __I915_REG_OP(read_notrace, dev_priv, (reg__))
>>   #define I915_WRITE_NOTRACE(reg__, val__) __I915_REG_OP(write_notrace, dev_priv, (reg__), (val__))
>>   
>> -/* Be very careful with read/write 64-bit values. On 32-bit machines, they
>> - * will be implemented using 2 32-bit writes in an arbitrary order with
>> - * an arbitrary delay between them. This can cause the hardware to
>> - * act upon the intermediate value, possibly leading to corruption and
>> - * machine death. For this reason we do not support I915_WRITE64, or
>> - * dev_priv->uncore.funcs.mmio_writeq.
>> - *
>> - * When reading a 64-bit value as two 32-bit values, the delay may cause
>> - * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
>> - * occasionally a 64-bit register does not actualy support a full readq
>> - * and must be read using two 32-bit reads.
>> - *
>> - * You have been warned.
> 
> We are no longer warned?

Clue is in the word duplicated in the commit message. ;) The exact same 
comment exists over in intel_uncore.h above 64-bit accessors and 
intel_uncore_read_2x32.

Regards,

Tvrtko