[Intel-gfx] [PATCH v2] drm/i915: Add Wa_1409120013:icl,ehl

[Matt Roper]

On Wed, Jun 12, 2019 at 11:16:02AM -0700, Matt Roper wrote:
> This chicken bit should be set before enabling FBC to avoid screen
> corruption when the plane size has odd vertical and horizontal
> dimensions.  It is safe to leave the bit set even when FBC is disabled.
> 
> v2:
>  - The bspec's name for this bit on these platforms ("Spare 14") is
>    pretty meaningless.  Let's rename the bit definition to something
>    that more accurately reflects what the bit really does.  (Clint)

Woops, looks like you also had a comment about the register already
being defined farther down that I didn't see when I first read your
email.  I'll send a v3 shortly.


Matt

> 
> Cc: Clinton Taylor <Clinton.A.Taylor at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 2 ++
>  drivers/gpu/drm/i915/intel_fbc.c | 4 ++++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index edf9f93934a1..54654a578c84 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3150,6 +3150,8 @@ enum i915_power_well_id {
>  
>  /* Framebuffer compression for Ironlake */
>  #define ILK_DPFC_CB_BASE	_MMIO(0x43200)
> +#define ILK_DPFC_CHICKEN	_MMIO(0x43224)
> +#define   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL	REG_BIT(14)
>  #define ILK_DPFC_CONTROL	_MMIO(0x43208)
>  #define   FBC_CTL_FALSE_COLOR	(1 << 10)
>  /* The bit 28-8 is reserved */
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 5679f2fffb7c..d36cada2cc7d 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -344,6 +344,10 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>  			   HSW_FBCQ_DIS);
>  	}
>  
> +	if (IS_GEN(dev_priv, 11))
> +		/* Wa_1409120013:icl,ehl */
> +		I915_WRITE(ILK_DPFC_CHICKEN, ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> +
>  	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
>  
>  	intel_fbc_recompress(dev_priv);
> -- 
> 2.14.5
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795