[Intel-gfx] [PATCH 4/4] drm/i915: Add whitelist workarounds for ICL

[Tvrtko Ursulin]

On 14/06/2019 01:28, Robert M. Fosha wrote:
> From: John Harrison <John.C.Harrison at Intel.com>
> 
> Updated whitelist table for ICL.
> 
> Signed-off-by: John Harrison <John.C.Harrison at Intel.com>
> Signed-off-by: Robert M. Fosha <robert.m.fosha at intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 87 +++++++++++++++++++--
>   1 file changed, 79 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 60bd515edaf1..aa99fb3ffbcb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1146,17 +1146,88 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>   {
>   	struct i915_wa_list *w = &engine->whitelist;
>   
> -	if (engine->class != RENDER_CLASS)
> -		return;
> +	switch (engine->class) {
> +	case RENDER_CLASS:
> +		/* WaSendPushConstantsFromMMIO:icl */
> +		whitelist_reg_ext(w, COMMON_SLICE_CHICKEN2,
> +				  RING_FORCE_TO_NONPRIV_RW);
>   
> -	/* WaAllowUMDToModifyHalfSliceChicken7:icl */
> -	whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
> +		/* WaAllowUMDToModifyHalfSliceChicken7:icl */
> +		whitelist_reg_ext(w, GEN9_HALF_SLICE_CHICKEN7,
> +				  RING_FORCE_TO_NONPRIV_RW);
>   
> -	/* WaAllowUMDToModifySamplerMode:icl */
> -	whitelist_reg(w, GEN10_SAMPLER_MODE);
> +		/* WaAllowUMDToModifySamplerMode:icl */
> +		whitelist_reg_ext(w, GEN10_SAMPLER_MODE,
> +				  RING_FORCE_TO_NONPRIV_RW);
>   
> -	/* WaEnableStateCacheRedirectToCS:icl */
> -	whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
> +		/* WaEnableStateCacheRedirectToCS:icl */
> +		whitelist_reg_ext(w, GEN9_SLICE_COMMON_ECO_CHICKEN1,
> +				  RING_FORCE_TO_NONPRIV_RW);
> +
> +		/* WaAllowUMDToModifyHalfSliceChicken2:icl */
> +		whitelist_reg_ext(w, HALF_SLICE_CHICKEN2,
> +				  RING_FORCE_TO_NONPRIV_RW);
> +
> +		/* WaDisableMidObjectPreemptioninUMD:icl */
> +		whitelist_reg_ext(w, GEN8_CS_CHICKEN1,
> +				  RING_FORCE_TO_NONPRIV_RW);
> +
> +		/* FtrSSEUPowerGatingControlByUMD:icl */
> +		whitelist_reg_ext(w, _MMIO(0x20C8), RING_FORCE_TO_NONPRIV_RW);
> +
> +		/* WaUseOaReportTriggersForQuery:icl */
> +		whitelist_reg_ext(w, OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_RW);
> +
> +		/* WaAllowUmdWriteTRTTRootTable:icl */
> +		whitelist_reg_ext(w, _MMIO(0x4DE0), RING_FORCE_TO_NONPRIV_RW);
> +		whitelist_reg_ext(w, _MMIO(0x4DE4), RING_FORCE_TO_NONPRIV_RW);
> +
> +		/* CL_PRIMITIVE_COUNT/PS_INVOCATIONS_COUNT */
> +		whitelist_reg_ext(w, CL_PRIMITIVES_COUNT,
> +				  RING_FORCE_TO_NONPRIV_RD |
> +				  RING_FORCE_TO_NONPRIV_RANGE_4);
> +
> +		/* PS_DEPTH_COUNT */
> +		whitelist_reg_ext(w, PS_DEPTH_COUNT, RING_FORCE_TO_NONPRIV_RD |
> +				  RING_FORCE_TO_NONPRIV_RANGE_4);
> +
> +		/* EUMETRICS_EVENT_0 -> _5 */
> +		whitelist_reg_ext(w, _MMIO(0xD8C), RING_FORCE_TO_NONPRIV_RD);
> +		whitelist_reg_ext(w, _MMIO(0xD90), RING_FORCE_TO_NONPRIV_RD |
> +				  RING_FORCE_TO_NONPRIV_RANGE_4);
> +		whitelist_reg_ext(w, _MMIO(0xDA0), RING_FORCE_TO_NONPRIV_RD);
> +
> +		/* SRD_PERF_COUNTER */
> +		whitelist_reg_ext(w, _MMIO(0x64844), RING_FORCE_TO_NONPRIV_RD);
> +
> +		/* WaAllowUMDAccesstoOARegisters:icl */
> +		whitelist_reg_ext(w, _MMIO(0x28A0), RING_FORCE_TO_NONPRIV_RW);
> +		whitelist_reg_ext(w, OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_RW);
> +		break;
> +	case VIDEO_DECODE_CLASS:
> +		/* hucStatusRegOffset */
> +		whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
> +				  RING_FORCE_TO_NONPRIV_RD);
> +		/* hucUKernelHdrInfoRegOffset */
> +		whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
> +				  RING_FORCE_TO_NONPRIV_RD);
> +		/* hucStatus2RegOffset */
> +		whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
> +				  RING_FORCE_TO_NONPRIV_RD);
> +
> +		/* fall through */
> +	case VIDEO_ENHANCEMENT_CLASS:
> +		/* WATCHDOG_COUNT_CONTROL */
> +		whitelist_reg_ext(w, _MMIO(0x178 + engine->mmio_base),
> +				  RING_FORCE_TO_NONPRIV_RD);
> +
> +		/* WATCHDOG_COUNT_THRESHOLD */
> +		whitelist_reg_ext(w, _MMIO(0x17C + engine->mmio_base),
> +				  RING_FORCE_TO_NONPRIV_RD);
> +		break;
> +	default:
> +		break;
> +	}
>   }
>   
>   void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> 

Again I suggest not using whitelist_reg_ext where not required. With 
that changed:

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Regards,

Tvrtko