[Intel-gfx] [PATCH 15/23] drm/i915: Sanitize the TypeC FIA lane configuration decoding

[Imre Deak]

On Tue, Jun 18, 2019 at 07:39:09PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 04, 2019 at 05:58:18PM +0300, Imre Deak wrote:
> > Use hex numbers, since that makes more sense when decoding a bit pattern.
> > 
> > No functional change.
> > 
> > Suggested-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > Cc: Animesh Manna <animesh.manna at intel.com>
> > Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak at intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_tc.c | 15 ++++++++-------
> >  1 file changed, 8 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_tc.c b/drivers/gpu/drm/i915/intel_tc.c
> > index fc0341dc50c5..4b2f525bc2a6 100644
> > --- a/drivers/gpu/drm/i915/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/intel_tc.c
> > @@ -72,15 +72,16 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> >  	switch (lane_info) {
> >  	default:
> >  		MISSING_CASE(lane_info);
> > -	case 1:
> > -	case 2:
> > -	case 4:
> > -	case 8:
> > +		/* fall-through */
> > +	case 0x1:
> > +	case 0x2:
> > +	case 0x4:
> > +	case 0x8:
> >  		return 1;
> > -	case 3:
> > -	case 12:
> > +	case 0x3:
> > +	case 0xc:
> >  		return 2;
> > -	case 15:
> > +	case 0xf:
> >  		return 4;
> >  	}
> 
> Still looks like a hand rolled hweight() to me ;)

Thought about that, but then we'd miss undefined encodings.

> 
> >  }
> > -- 
> > 2.17.1
> 
> -- 
> Ville Syrjälä
> Intel