[Intel-gfx] [PATCH 1/2] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT

[Lionel Landwerlin]

CFL:C0+ changed the status of those registers which are now
blacklisted by default.

This is breaking a number of CTS tests on GL & Vulkan :

  KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations (GL)

  dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.* (Vulkan)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 165b0a45e009..90df58ed1486 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1068,6 +1068,12 @@ static void glk_whitelist_build(struct i915_wa_list *w)
 static void cfl_whitelist_build(struct i915_wa_list *w)
 {
 	gen9_whitelist_build(w);
+
+	/* WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml */
+	whitelist_reg(w, PS_DEPTH_COUNT);
+	whitelist_reg(w, PS_DEPTH_COUNT_UDW);
+	whitelist_reg(w, PS_INVOCATION_COUNT);
+	whitelist_reg(w, PS_INVOCATION_COUNT_UDW);
 }
 
 static void cnl_whitelist_build(struct i915_wa_list *w)
-- 
2.21.0.392.gf8f6787159e