[Intel-gfx] [PATCH 17/19] drm/i915/gt: Drop stale commentary for timeline density

[Chris Wilson]

We no longer allocate a continguous set of timeline ids for all engines
upon creation, so we no longer should assume that the timelines are
density allocated within a context. Hopefully, still dense enough for us
to take advantage of the compressed radix tree.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_timeline.c | 14 ++------------
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 030bcd2249e9..995406bde27e 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -210,21 +210,11 @@ int intel_timeline_init(struct intel_timeline *timeline,
 {
 	void *vaddr;
 
-	/*
-	 * Ideally we want a set of engines on a single leaf as we expect
-	 * to mostly be tracking synchronisation between engines. It is not
-	 * a huge issue if this is not the case, but we may want to mitigate
-	 * any page crossing penalties if they become an issue.
-	 *
-	 * Called during early_init before we know how many engines there are.
-	 */
-	BUILD_BUG_ON(KSYNCMAP < I915_NUM_ENGINES);
-
-	timeline->gt = gt;
-
 	kref_init(&timeline->kref);
 	atomic_set(&timeline->pin_count, 0);
 
+	timeline->gt = gt;
+
 	timeline->has_initial_breadcrumb = !hwsp;
 	timeline->hwsp_cacheline = NULL;
 
-- 
2.20.1