[Intel-gfx] [PATCH 10/28] drm/i915/tgl: Add power well support
Lucas De Marchi
lucas.demarchi at intel.com
Thu Jun 27 20:22:36 UTC 2019
On Thu, Jun 27, 2019 at 12:31:30PM -0700, Jose Souza wrote:
>On Tue, 2019-06-25 at 10:54 -0700, Lucas De Marchi wrote:
>> From: Imre Deak <imre.deak at intel.com>
>>
>> The patch adds the new power wells introduced by TGL (GEN 12) and
>> maps these to existing/new power domains. The changes for GEN 12 wrt
>> to GEN 11 are the following:
>>
>> - Transcoder#EDP removed from power well#1 (Transcoder#A used in
>> low-power mode instead)
>> - Transcoder#A is now backed by power well#1 instead of power well#3
>> - The DDI#B/C combo PHY ports are now backed by power well#1 instead
>> of
>> power well#3
>> - New power well#5 added for pipe#D functionality (TODO)
>> - 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
>> specific IO power wells (only for the non-TBT modes) and 4 port
>> specific AUX power wells (2-2 for TBT vs. non-TBT modes)
>> - Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
>> eDP and MIPI DSI (TODO)
>>
>> On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
>> BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL
>> we
>> have the following naming for ports:
>>
>> - Combo PHYs (native DP/HDMI):
>> DDI#A-B
>> - TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
>> DDI#C-F
>>
>> Starting from GEN 12 we have the following naming for ports:
>> - Combo PHYs (native DP/HDMI):
>> DDI#A-C
>> - TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
>> DDI TC#1-6
>>
>> To save some space in the power domain enum the power domain naming
>> in
>> the driver reflects the above change, that is power domains TC#1-3
>> are
>> added as aliases for DDI#D-F and new power domains are reserved for
>> TC#4-6.
>>
>> Cc: Anusha Srivatsa <anusha.srivatsa at intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
>> Cc: José Roberto de Souza <jose.souza at intel.com>
>> Signed-off-by: Imre Deak <imre.deak at intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
>> ---
>> .../drm/i915/display/intel_display_power.c | 474
>> +++++++++++++++++-
>> .../drm/i915/display/intel_display_power.h | 26 +-
>> drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
>> drivers/gpu/drm/i915/i915_reg.h | 18 +
>> 4 files changed, 502 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index c93ad512014c..20b2009cecc6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -22,8 +22,11 @@ bool intel_display_power_well_is_enabled(struct
>> drm_i915_private *dev_priv,
>> enum i915_power_well_id
>> power_well_id);
>>
>> const char *
>> -intel_display_power_domain_str(enum intel_display_power_domain
>> domain)
>> +intel_display_power_domain_str(struct drm_i915_private *i915,
>> + enum intel_display_power_domain domain)
>> {
>> + bool ddi_tc_ports = IS_GEN(i915, 12);
>> +
>> switch (domain) {
>> case POWER_DOMAIN_DISPLAY_CORE:
>> return "DISPLAY_CORE";
>> @@ -60,11 +63,23 @@ intel_display_power_domain_str(enum
>> intel_display_power_domain domain)
>> case POWER_DOMAIN_PORT_DDI_C_LANES:
>> return "PORT_DDI_C_LANES";
>> case POWER_DOMAIN_PORT_DDI_D_LANES:
>> - return "PORT_DDI_D_LANES";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
>> + POWER_DOMAIN_PORT_DDI_TC1_LANES);
>> + return ddi_tc_ports ? "PORT_DDI_TC1_LANES" :
>> "PORT_DDI_D_LANES";
>> case POWER_DOMAIN_PORT_DDI_E_LANES:
>> - return "PORT_DDI_E_LANES";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
>> + POWER_DOMAIN_PORT_DDI_TC2_LANES);
>> + return ddi_tc_ports ? "PORT_DDI_TC2_LANES" :
>> "PORT_DDI_E_LANES";
>> case POWER_DOMAIN_PORT_DDI_F_LANES:
>> - return "PORT_DDI_F_LANES";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
>> + POWER_DOMAIN_PORT_DDI_TC3_LANES);
>> + return ddi_tc_ports ? "PORT_DDI_TC3_LANES" :
>> "PORT_DDI_F_LANES";
>> + case POWER_DOMAIN_PORT_DDI_TC4_LANES:
>> + return "PORT_DDI_TC4_LANES";
>> + case POWER_DOMAIN_PORT_DDI_TC5_LANES:
>> + return "PORT_DDI_TC5_LANES";
>> + case POWER_DOMAIN_PORT_DDI_TC6_LANES:
>> + return "PORT_DDI_TC6_LANES";
>> case POWER_DOMAIN_PORT_DDI_A_IO:
>> return "PORT_DDI_A_IO";
>> case POWER_DOMAIN_PORT_DDI_B_IO:
>> @@ -72,11 +87,23 @@ intel_display_power_domain_str(enum
>> intel_display_power_domain domain)
>> case POWER_DOMAIN_PORT_DDI_C_IO:
>> return "PORT_DDI_C_IO";
>> case POWER_DOMAIN_PORT_DDI_D_IO:
>> - return "PORT_DDI_D_IO";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
>> + POWER_DOMAIN_PORT_DDI_TC1_IO);
>> + return ddi_tc_ports ? "PORT_DDI_TC1_IO" :
>> "PORT_DDI_D_IO";
>> case POWER_DOMAIN_PORT_DDI_E_IO:
>> - return "PORT_DDI_E_IO";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
>> + POWER_DOMAIN_PORT_DDI_TC2_IO);
>> + return ddi_tc_ports ? "PORT_DDI_TC2_IO" :
>> "PORT_DDI_E_IO";
>> case POWER_DOMAIN_PORT_DDI_F_IO:
>> - return "PORT_DDI_F_IO";
>> + BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
>> + POWER_DOMAIN_PORT_DDI_TC3_IO);
>> + return ddi_tc_ports ? "PORT_DDI_TC3_IO" :
>> "PORT_DDI_F_IO";
>> + case POWER_DOMAIN_PORT_DDI_TC4_IO:
>> + return "PORT_DDI_TC4_IO";
>> + case POWER_DOMAIN_PORT_DDI_TC5_IO:
>> + return "PORT_DDI_TC5_IO";
>> + case POWER_DOMAIN_PORT_DDI_TC6_IO:
>> + return "PORT_DDI_TC6_IO";
>> case POWER_DOMAIN_PORT_DSI:
>> return "PORT_DSI";
>> case POWER_DOMAIN_PORT_CRT:
>> @@ -94,11 +121,20 @@ intel_display_power_domain_str(enum
>> intel_display_power_domain domain)
>> case POWER_DOMAIN_AUX_C:
>> return "AUX_C";
>> case POWER_DOMAIN_AUX_D:
>> - return "AUX_D";
>> + BUILD_BUG_ON(POWER_DOMAIN_AUX_D !=
>> POWER_DOMAIN_AUX_TC1);
>> + return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
>> case POWER_DOMAIN_AUX_E:
>> - return "AUX_E";
>> + BUILD_BUG_ON(POWER_DOMAIN_AUX_E !=
>> POWER_DOMAIN_AUX_TC2);
>> + return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
>> case POWER_DOMAIN_AUX_F:
>> - return "AUX_F";
>> + BUILD_BUG_ON(POWER_DOMAIN_AUX_F !=
>> POWER_DOMAIN_AUX_TC3);
>> + return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
>> + case POWER_DOMAIN_AUX_TC4:
>> + return "AUX_TC4";
>> + case POWER_DOMAIN_AUX_TC5:
>> + return "AUX_TC5";
>> + case POWER_DOMAIN_AUX_TC6:
>> + return "AUX_TC6";
>> case POWER_DOMAIN_AUX_IO_A:
>> return "AUX_IO_A";
>> case POWER_DOMAIN_AUX_TBT1:
>> @@ -109,6 +145,10 @@ intel_display_power_domain_str(enum
>> intel_display_power_domain domain)
>> return "AUX_TBT3";
>> case POWER_DOMAIN_AUX_TBT4:
>> return "AUX_TBT4";
>> + case POWER_DOMAIN_AUX_TBT5:
>> + return "AUX_TBT5";
>> + case POWER_DOMAIN_AUX_TBT6:
>> + return "AUX_TBT6";
>> case POWER_DOMAIN_GMBUS:
>> return "GMBUS";
>> case POWER_DOMAIN_INIT:
>> @@ -1568,12 +1608,15 @@ __async_put_domains_state_ok(struct
>> i915_power_domains *power_domains)
>> static void print_power_domains(struct i915_power_domains
>> *power_domains,
>> const char *prefix, u64 mask)
>> {
>> + struct drm_i915_private *i915 =
>> + container_of(power_domains, struct drm_i915_private,
>> + power_domains);
>> enum intel_display_power_domain domain;
>>
>> DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
>> for_each_power_domain(domain, mask)
>> DRM_DEBUG_DRIVER("%s use_count %d\n",
>> - intel_display_power_domain_str(domain)
>> ,
>> + intel_display_power_domain_str(i915,
>> domain),
>> power_domains-
>> >domain_use_count[domain]);
>> }
>>
>> @@ -1743,7 +1786,7 @@ __intel_display_power_put_domain(struct
>> drm_i915_private *dev_priv,
>> {
>> struct i915_power_domains *power_domains;
>> struct i915_power_well *power_well;
>> - const char *name = intel_display_power_domain_str(domain);
>> + const char *name = intel_display_power_domain_str(dev_priv,
>> domain);
>>
>> power_domains = &dev_priv->power_domains;
>>
>> @@ -2307,11 +2350,14 @@ void intel_display_power_put(struct
>> drm_i915_private *dev_priv,
>> * ICL PW_1/PG_1 domains (HW/DMC control):
>> * - DBUF function
>> * - PIPE_A and its planes, except VGA
>> - * - transcoder EDP + PSR
>> + * - GEN 11: transcoder EDP + PSR
>> + * GEN 12: transcoder A + PSR
>> * - transcoder DSI
>> - * - DDI_A
>> + * - GEN 11: DDI_A
>> + * GEN 12: DDI_A-C
>> * - FBC
>> */
>> +/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
>> #define ICL_PW_4_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PIPE_C) | \
>> BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
>> @@ -2346,22 +2392,67 @@ void intel_display_power_put(struct
>> drm_i915_private *dev_priv,
>> BIT_ULL(POWER_DOMAIN_VGA) | \
>> BIT_ULL(POWER_DOMAIN_AUDIO) | \
>> BIT_ULL(POWER_DOMAIN_INIT))
>> +#define TGL_PW_3_POWER_DOMAINS ( \
>> + ICL_PW_4_POWER_DOMAINS | \
>> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
>> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
>> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
>> + /* TODO: TRANSCODER_D */ \
>> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) | \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC1) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC2) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC3) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC4) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC5) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC6) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
>> + BIT_ULL(POWER_DOMAIN_VGA) | \
>> + BIT_ULL(POWER_DOMAIN_AUDIO) | \
>> + BIT_ULL(POWER_DOMAIN_INIT))
>> /*
>> * - transcoder WD
>> * - KVMR (HW control)
>> */
>> #define ICL_PW_2_POWER_DOMAINS ( \
>> ICL_PW_3_POWER_DOMAINS | \
>> - BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
>> + BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
>> + BIT_ULL(POWER_DOMAIN_INIT))
>> +#define TGL_PW_2_POWER_DOMAINS ( \
>> + TGL_PW_3_POWER_DOMAINS | \
>> + BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
>
>There is no POWER_DOMAIN_TRANSCODER_EDP_VDSC on TGL, maybe reorder the
>patches to have "drm/i915/tgl: Add TRANSCODER_A_VDSC power domain"
>first then you can add TRANSCODER_A_VDSC here.
makes sense,
thanks
Lucas De Marchi
>
>> BIT_ULL(POWER_DOMAIN_INIT))
>> /*
>> * - KVMR (HW control)
>> + * - GEN 11: eDP/DSI VDSC
>> + * - GEN 12: PIPE A VDSC/joining
>> */
>> #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
>> ICL_PW_2_POWER_DOMAINS | \
>> BIT_ULL(POWER_DOMAIN_MODESET) | \
>> BIT_ULL(POWER_DOMAIN_AUX_A) | \
>> BIT_ULL(POWER_DOMAIN_INIT))
>> +#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
>> + TGL_PW_2_POWER_DOMAINS | \
>> + BIT_ULL(POWER_DOMAIN_MODESET) | \
>> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
>> + BIT_ULL(POWER_DOMAIN_INIT))
>>
>> #define ICL_DDI_IO_A_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
>> @@ -2371,10 +2462,22 @@ void intel_display_power_put(struct
>> drm_i915_private *dev_priv,
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
>> #define ICL_DDI_IO_D_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
>> +#define TGL_DDI_IO_TC1_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
>> #define ICL_DDI_IO_E_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
>> +#define TGL_DDI_IO_TC2_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
>> #define ICL_DDI_IO_F_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
>> +#define TGL_DDI_IO_TC3_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
>> +#define TGL_DDI_IO_TC4_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
>> +#define TGL_DDI_IO_TC5_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
>> +#define TGL_DDI_IO_TC6_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
>>
>> #define ICL_AUX_A_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
>> @@ -2385,10 +2488,22 @@ void intel_display_power_put(struct
>> drm_i915_private *dev_priv,
>> BIT_ULL(POWER_DOMAIN_AUX_C))
>> #define ICL_AUX_D_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_D))
>> +#define TGL_AUX_TC1_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC1))
>> #define ICL_AUX_E_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_E))
>> +#define TGL_AUX_TC2_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC2))
>> #define ICL_AUX_F_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_F))
>> +#define TGL_AUX_TC3_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC3))
>> +#define TGL_AUX_TC4_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC4))
>> +#define TGL_AUX_TC5_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC5))
>> +#define TGL_AUX_TC6_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TC6))
>> #define ICL_AUX_TBT1_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_TBT1))
>> #define ICL_AUX_TBT2_IO_POWER_DOMAINS ( \
>> @@ -2397,6 +2512,10 @@ void intel_display_power_put(struct
>> drm_i915_private *dev_priv,
>> BIT_ULL(POWER_DOMAIN_AUX_TBT3))
>> #define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
>> BIT_ULL(POWER_DOMAIN_AUX_TBT4))
>> +#define TGL_AUX_TBT5_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT5))
>> +#define TGL_AUX_TBT6_IO_POWER_DOMAINS ( \
>> + BIT_ULL(POWER_DOMAIN_AUX_TBT6))
>>
>> static const struct i915_power_well_ops
>> i9xx_always_on_power_well_ops = {
>> .sync_hw = i9xx_power_well_sync_hw_noop,
>> @@ -3355,6 +3474,324 @@ static const struct i915_power_well_desc
>> icl_power_wells[] = {
>> },
>> };
>>
>> +static const struct i915_power_well_desc tgl_power_wells[] = {
>> + {
>> + .name = "always-on",
>> + .always_on = true,
>> + .domains = POWER_DOMAIN_MASK,
>> + .ops = &i9xx_always_on_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + },
>> + {
>> + .name = "power well 1",
>> + /* Handled by the DMC firmware */
>> + .always_on = true,
>> + .domains = 0,
>> + .ops = &hsw_power_well_ops,
>> + .id = SKL_DISP_PW_1,
>> + {
>> + .hsw.regs = &hsw_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_PW_1,
>> + .hsw.has_fuses = true,
>> + },
>> + },
>> + {
>> + .name = "DC off",
>> + .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
>> + .ops = &gen9_dc_off_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + },
>> + {
>> + .name = "power well 2",
>> + .domains = TGL_PW_2_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = SKL_DISP_PW_2,
>> + {
>> + .hsw.regs = &hsw_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
>> + .hsw.has_fuses = true,
>> + },
>> + },
>> + {
>> + .name = "power well 3",
>> + .domains = TGL_PW_3_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &hsw_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_PW_3,
>> + .hsw.irq_pipe_mask = BIT(PIPE_B),
>> + .hsw.has_vga = true,
>> + .hsw.has_fuses = true,
>> + },
>> + },
>> + {
>> + .name = "DDI A IO",
>> + .domains = ICL_DDI_IO_A_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
>> + }
>> + },
>> + {
>> + .name = "DDI B IO",
>> + .domains = ICL_DDI_IO_B_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
>> + }
>> + },
>> + {
>> + .name = "DDI C IO",
>> + .domains = ICL_DDI_IO_C_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
>> + }
>> + },
>> + {
>> + .name = "DDI TC1 IO",
>> + .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
>> + },
>> + },
>> + {
>> + .name = "DDI TC2 IO",
>> + .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
>> + },
>> + },
>> + {
>> + .name = "DDI TC3 IO",
>> + .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
>> + },
>> + },
>> + {
>> + .name = "DDI TC4 IO",
>> + .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
>> + },
>> + },
>> + {
>> + .name = "DDI TC5 IO",
>> + .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
>> + },
>> + },
>> + {
>> + .name = "DDI TC6 IO",
>> + .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_ddi_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
>> + },
>> + },
>> + {
>> + .name = "AUX A",
>> + .domains = ICL_AUX_A_IO_POWER_DOMAINS,
>> + .ops = &icl_combo_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
>> + },
>> + },
>> + {
>> + .name = "AUX B",
>> + .domains = ICL_AUX_B_IO_POWER_DOMAINS,
>> + .ops = &icl_combo_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
>> + },
>> + },
>> + {
>> + .name = "AUX C",
>> + .domains = ICL_AUX_C_IO_POWER_DOMAINS,
>> + .ops = &icl_combo_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
>> + },
>> + },
>> + {
>> + .name = "AUX TC1",
>> + .domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC2",
>> + .domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC3",
>> + .domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC4",
>> + .domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC5",
>> + .domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TC6",
>> + .domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
>> + .ops = &icl_tc_phy_aux_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
>> + .hsw.is_tc_tbt = false,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT1",
>> + .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT2",
>> + .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT3",
>> + .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT4",
>> + .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT5",
>> + .domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "AUX TBT6",
>> + .domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &icl_aux_power_well_regs,
>> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
>> + .hsw.is_tc_tbt = true,
>> + },
>> + },
>> + {
>> + .name = "power well 4",
>> + .domains = ICL_PW_4_POWER_DOMAINS,
>> + .ops = &hsw_power_well_ops,
>> + .id = DISP_PW_ID_NONE,
>> + {
>> + .hsw.regs = &hsw_power_well_regs,
>> + .hsw.idx = ICL_PW_CTL_IDX_PW_4,
>> + .hsw.has_fuses = true,
>> + .hsw.irq_pipe_mask = BIT(PIPE_C),
>> + }
>> + },
>> + /* TODO: power well 5 for pipe D */
>> +};
>> +
>> static int
>> sanitize_disable_power_well_option(const struct drm_i915_private
>> *dev_priv,
>> int disable_power_well)
>> @@ -3482,7 +3919,9 @@ int intel_power_domains_init(struct
>> drm_i915_private *dev_priv)
>> * The enabling order will be from lower to higher indexed
>> wells,
>> * the disabling order is reversed.
>> */
>> - if (IS_GEN(dev_priv, 11)) {
>> + if (IS_GEN(dev_priv, 12)) {
>> + err = set_power_wells(power_domains, tgl_power_wells);
>> + } else if (IS_GEN(dev_priv, 11)) {
>> err = set_power_wells(power_domains, icl_power_wells);
>> } else if (IS_CANNONLAKE(dev_priv)) {
>> err = set_power_wells(power_domains, cnl_power_wells);
>> @@ -4546,7 +4985,8 @@ static void
>> intel_power_domains_dump_info(struct drm_i915_private *i915)
>>
>> for_each_power_domain(domain, power_well->desc-
>> >domains)
>> DRM_DEBUG_DRIVER(" %-23s %d\n",
>> - intel_display_power_domain_str
>> (domain),
>> + intel_display_power_domain_str
>> (i915,
>> +
>> domain),
>> power_domains-
>> >domain_use_count[domain]);
>> }
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
>> b/drivers/gpu/drm/i915/display/intel_display_power.h
>> index ff57b0a7fe59..8f81b769bc2e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> @@ -32,14 +32,29 @@ enum intel_display_power_domain {
>> POWER_DOMAIN_PORT_DDI_B_LANES,
>> POWER_DOMAIN_PORT_DDI_C_LANES,
>> POWER_DOMAIN_PORT_DDI_D_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC1_LANES =
>> POWER_DOMAIN_PORT_DDI_D_LANES,
>> POWER_DOMAIN_PORT_DDI_E_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC2_LANES =
>> POWER_DOMAIN_PORT_DDI_E_LANES,
>> POWER_DOMAIN_PORT_DDI_F_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC3_LANES =
>> POWER_DOMAIN_PORT_DDI_F_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC4_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC5_LANES,
>> + POWER_DOMAIN_PORT_DDI_TC6_LANES,
>> POWER_DOMAIN_PORT_DDI_A_IO,
>> POWER_DOMAIN_PORT_DDI_B_IO,
>> POWER_DOMAIN_PORT_DDI_C_IO,
>> POWER_DOMAIN_PORT_DDI_D_IO,
>> + POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
>> POWER_DOMAIN_PORT_DDI_E_IO,
>> + POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
>> POWER_DOMAIN_PORT_DDI_F_IO,
>> + POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
>> + POWER_DOMAIN_PORT_DDI_G_IO,
>> + POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
>> + POWER_DOMAIN_PORT_DDI_H_IO,
>> + POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
>> + POWER_DOMAIN_PORT_DDI_I_IO,
>> + POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
>> POWER_DOMAIN_PORT_DSI,
>> POWER_DOMAIN_PORT_CRT,
>> POWER_DOMAIN_PORT_OTHER,
>> @@ -49,13 +64,21 @@ enum intel_display_power_domain {
>> POWER_DOMAIN_AUX_B,
>> POWER_DOMAIN_AUX_C,
>> POWER_DOMAIN_AUX_D,
>> + POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
>> POWER_DOMAIN_AUX_E,
>> + POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
>> POWER_DOMAIN_AUX_F,
>> + POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
>> + POWER_DOMAIN_AUX_TC4,
>> + POWER_DOMAIN_AUX_TC5,
>> + POWER_DOMAIN_AUX_TC6,
>> POWER_DOMAIN_AUX_IO_A,
>> POWER_DOMAIN_AUX_TBT1,
>> POWER_DOMAIN_AUX_TBT2,
>> POWER_DOMAIN_AUX_TBT3,
>> POWER_DOMAIN_AUX_TBT4,
>> + POWER_DOMAIN_AUX_TBT5,
>> + POWER_DOMAIN_AUX_TBT6,
>> POWER_DOMAIN_GMBUS,
>> POWER_DOMAIN_MODESET,
>> POWER_DOMAIN_GT_IRQ,
>> @@ -227,7 +250,8 @@ void bxt_display_core_init(struct
>> drm_i915_private *dev_priv, bool resume);
>> void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
>>
>> const char *
>> -intel_display_power_domain_str(enum intel_display_power_domain
>> domain);
>> +intel_display_power_domain_str(struct drm_i915_private *i915,
>> + enum intel_display_power_domain domain);
>>
>> bool intel_display_power_is_enabled(struct drm_i915_private
>> *dev_priv,
>> enum intel_display_power_domain
>> domain);
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index eeecdad0e3ca..5247fa69dfec 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -2479,7 +2479,8 @@ static int i915_power_domain_info(struct
>> seq_file *m, void *unused)
>>
>> for_each_power_domain(power_domain, power_well->desc-
>> >domains)
>> seq_printf(m, " %-23s %d\n",
>> - intel_display_power_domain_str(power_d
>> omain),
>> + intel_display_power_domain_str(dev_pri
>> v,
>> + power_d
>> omain),
>> power_domains-
>> >domain_use_count[power_domain]);
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 95fdc8dbca31..a2010b30ca89 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9141,13 +9141,25 @@ enum {
>> #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
>> #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
>> #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
>> +#define TGL_PW_CTL_IDX_AUX_TBT6 14
>> +#define TGL_PW_CTL_IDX_AUX_TBT5 13
>> +#define TGL_PW_CTL_IDX_AUX_TBT4 12
>> #define ICL_PW_CTL_IDX_AUX_TBT4 11
>> +#define TGL_PW_CTL_IDX_AUX_TBT3 11
>> #define ICL_PW_CTL_IDX_AUX_TBT3 10
>> +#define TGL_PW_CTL_IDX_AUX_TBT2 10
>> #define ICL_PW_CTL_IDX_AUX_TBT2 9
>> +#define TGL_PW_CTL_IDX_AUX_TBT1 9
>> #define ICL_PW_CTL_IDX_AUX_TBT1 8
>> +#define TGL_PW_CTL_IDX_AUX_TC6 8
>> +#define TGL_PW_CTL_IDX_AUX_TC5 7
>> +#define TGL_PW_CTL_IDX_AUX_TC4 6
>> #define ICL_PW_CTL_IDX_AUX_F 5
>> +#define TGL_PW_CTL_IDX_AUX_TC3 5
>> #define ICL_PW_CTL_IDX_AUX_E 4
>> +#define TGL_PW_CTL_IDX_AUX_TC2 4
>> #define ICL_PW_CTL_IDX_AUX_D 3
>> +#define TGL_PW_CTL_IDX_AUX_TC1 3
>> #define ICL_PW_CTL_IDX_AUX_C 2
>> #define ICL_PW_CTL_IDX_AUX_B 1
>> #define ICL_PW_CTL_IDX_AUX_A 0
>> @@ -9155,9 +9167,15 @@ enum {
>> #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
>> #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
>> #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
>> +#define TGL_PW_CTL_IDX_DDI_TC6 8
>> +#define TGL_PW_CTL_IDX_DDI_TC5 7
>> +#define TGL_PW_CTL_IDX_DDI_TC4 6
>> #define ICL_PW_CTL_IDX_DDI_F 5
>> +#define TGL_PW_CTL_IDX_DDI_TC3 5
>> #define ICL_PW_CTL_IDX_DDI_E 4
>> +#define TGL_PW_CTL_IDX_DDI_TC2 4
>> #define ICL_PW_CTL_IDX_DDI_D 3
>> +#define TGL_PW_CTL_IDX_DDI_TC1 3
>> #define ICL_PW_CTL_IDX_DDI_C 2
>> #define ICL_PW_CTL_IDX_DDI_B 1
>> #define ICL_PW_CTL_IDX_DDI_A 0
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