[Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access

[Chris Wilson]

Quoting Dale B Stimson (2019-03-01 00:36:10)
> On Sat, Feb 23, 2019 at 09:45:10AM +0000, Chris Wilson wrote:
> > Verify that our list of nonpriv registers exist and are writable.
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > Cc: Dale B Stimson <dale.b.stimson at intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> > ---
> >  tests/i915/gem_ctx_isolation.c | 164 +++++++++++++++++++++++++++------
> >  1 file changed, 135 insertions(+), 29 deletions(-)
> > 
> > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> > index 839d49ad..991a997f 100644
> > --- a/tests/i915/gem_ctx_isolation.c
> > +++ b/tests/i915/gem_ctx_isolation.c
> > @@ -59,16 +59,23 @@ enum {
> >  
> >  static const struct named_register {
> >       const char *name;
> > -     unsigned int gen_mask;
> > -     unsigned int engine_mask;
> > -     uint32_t offset;
> > +     unsigned int gen_mask; /* on which gen the register exists */
> > +     unsigned int engine_mask; /* preferred engine / powerwell */
> > +     uint32_t offset; /* address of register, from bottom of mmio bar */
> >       uint32_t count;
> >       uint32_t ignore_bits;
> > +     uint32_t write_mask; /* some registers bits do not exist */
> >       bool masked;
> >  } nonpriv_registers[] = {
> >       { "NOPID", NOCTX, RCS0, 0x2094 },
> >       { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
> > -     { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
> > +     {
> > +             "INSTPM",
> > +             GEN6, RCS0, 0x20c0,
> > +             .ignore_bits = BIT(8) /* ro counter */,
> > +             .write_mask = BIT(8) /* rsvd varies between gen */,
> > +             .masked = true,
> > +     },
> >       { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
> >       { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
> >       { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
> > @@ -78,7 +85,7 @@ static const struct named_register {
> >       { "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
> >       { "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
> >       { "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
> > -     { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
> > +     { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
> 
> I can't find a reason for adding ".write_mask = ~0x3".

Observed behaviour on byt.

> >       { "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
> > -     { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
> > -     { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
> > -     { "GT_MODE", GEN8, RCS0, 0x7008 },
> > -     { "L3_Config", GEN7, RCS0, 0x7034 },
> > -     { "TD_CTL", GEN8, RCS0, 0xe400 },
> > +     { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> > +     { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> > +     { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> > +     { "L3_Config", GEN8, RCS0, 0x7034 },
> > +     { "TD_CTL", GEN8, RCS0, 0xe400, .masked = true },
> 
> It looks to me like TD_CTL should not be ".masked = true", as docs state
> "reserved" and "31:16 MBZ".

Ah, side-effect of not using asymmetric 31-16, 15-0.

Looks like it should be .write_mask=0xffff instead.
-Chris