[Intel-gfx] [PATCH 10/38] drm/i915: Store the BIT(engine->id) as the engine's mask
Tvrtko Ursulin
tvrtko.ursulin at linux.intel.com
Fri Mar 1 15:25:29 UTC 2019
On 01/03/2019 14:03, Chris Wilson wrote:
> In the next patch, we are introducing a broad virtual engine to encompass
> multiple physical engines, losing the 1:1 nature of BIT(engine->id). To
> reflect the broader set of engines implied by the virtual instance, lets
> store the full bitmask.
>
> v2: Use intel_engine_mask_t (s/ring_mask/engine_mask/)
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 39 +++++++++++--------
> drivers/gpu/drm/i915/i915_reset.c | 8 ++--
> drivers/gpu/drm/i915/intel_device_info.c | 6 +--
> drivers/gpu/drm/i915/intel_device_info.h | 6 +--
> drivers/gpu/drm/i915/intel_engine_cs.c | 15 ++++---
> drivers/gpu/drm/i915/intel_guc_submission.c | 4 +-
> drivers/gpu/drm/i915/intel_hangcheck.c | 8 ++--
> drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++++-----
> drivers/gpu/drm/i915/intel_ringbuffer.h | 11 ++----
> .../gpu/drm/i915/selftests/i915_gem_context.c | 6 +--
> drivers/gpu/drm/i915/selftests/i915_request.c | 2 +-
> drivers/gpu/drm/i915/selftests/intel_guc.c | 4 +-
> .../gpu/drm/i915/selftests/intel_hangcheck.c | 4 +-
> drivers/gpu/drm/i915/selftests/intel_lrc.c | 4 +-
> .../drm/i915/selftests/intel_workarounds.c | 2 +-
> drivers/gpu/drm/i915/selftests/mock_engine.c | 1 +
> .../gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
> 19 files changed, 75 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cf325a00d143..0dd680cdb9ce 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2099,7 +2099,7 @@ static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
>
> /* Iterator over subset of engines selected by mask */
> #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
> - for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
> + for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
> (tmp__) ? \
> ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
> 0;)
> @@ -2432,7 +2432,7 @@ static inline unsigned int i915_sg_segment_size(void)
> #define ALL_ENGINES (~0)
>
> #define HAS_ENGINE(dev_priv, id) \
> - (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
> + (!!(INTEL_INFO(dev_priv)->engine_mask & ENGINE_MASK(id)))
>
> #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
> #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 7e79691664e5..99022738cc89 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -798,7 +798,7 @@ static void gen8_initialize_pml4(struct i915_address_space *vm,
> */
> static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
> {
> - ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->vm.i915)->ring_mask;
> + ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->vm.i915)->engine_mask;
Could rename pd_dirty_rings as well.
> }
>
> /* Removes entries from a single page table, releasing it if it's empty.
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index a9211c370cd1..524f55771f23 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -94,7 +94,7 @@
> .gpu_reset_clobbers_display = true, \
> .hws_needs_physical = 1, \
> .unfenced_needs_alignment = 1, \
> - .ring_mask = RENDER_RING, \
> + .engine_mask = RENDER_RING, \
What RENDER_*RING* & co, while we are churning?
Could we use the not-much-remaining-used ENGINE_MASK in here? Like:
.engine_mask = ENGINE(RCS) | .. ;
> .has_snoop = true, \
> .has_coherent_ggtt = false, \
> GEN_DEFAULT_PIPEOFFSETS, \
> @@ -133,7 +133,7 @@ static const struct intel_device_info intel_i865g_info = {
> .num_pipes = 2, \
> .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> - .ring_mask = RENDER_RING, \
> + .engine_mask = RENDER_RING, \
> .has_snoop = true, \
> .has_coherent_ggtt = true, \
> GEN_DEFAULT_PIPEOFFSETS, \
> @@ -210,7 +210,7 @@ static const struct intel_device_info intel_pineview_info = {
> .display.has_hotplug = 1, \
> .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> - .ring_mask = RENDER_RING, \
> + .engine_mask = RENDER_RING, \
> .has_snoop = true, \
> .has_coherent_ggtt = true, \
> GEN_DEFAULT_PIPEOFFSETS, \
> @@ -239,7 +239,7 @@ static const struct intel_device_info intel_i965gm_info = {
> static const struct intel_device_info intel_g45_info = {
> GEN4_FEATURES,
> PLATFORM(INTEL_G45),
> - .ring_mask = RENDER_RING | BSD_RING,
> + .engine_mask = RENDER_RING | BSD_RING,
> .gpu_reset_clobbers_display = false,
> };
>
> @@ -249,7 +249,7 @@ static const struct intel_device_info intel_gm45_info = {
> .is_mobile = 1,
> .display.has_fbc = 1,
> .display.supports_tv = 1,
> - .ring_mask = RENDER_RING | BSD_RING,
> + .engine_mask = RENDER_RING | BSD_RING,
> .gpu_reset_clobbers_display = false,
> };
>
> @@ -257,7 +257,7 @@ static const struct intel_device_info intel_gm45_info = {
> GEN(5), \
> .num_pipes = 2, \
> .display.has_hotplug = 1, \
> - .ring_mask = RENDER_RING | BSD_RING, \
> + .engine_mask = RENDER_RING | BSD_RING, \
> .has_snoop = true, \
> .has_coherent_ggtt = true, \
> /* ilk does support rc6, but we do not implement [power] contexts */ \
> @@ -283,7 +283,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
> .num_pipes = 2, \
> .display.has_hotplug = 1, \
> .display.has_fbc = 1, \
> - .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
> + .engine_mask = RENDER_RING | BSD_RING | BLT_RING, \
> .has_coherent_ggtt = true, \
> .has_llc = 1, \
> .has_rc6 = 1, \
> @@ -328,7 +328,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
> .num_pipes = 3, \
> .display.has_hotplug = 1, \
> .display.has_fbc = 1, \
> - .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
> + .engine_mask = RENDER_RING | BSD_RING | BLT_RING, \
> .has_coherent_ggtt = true, \
> .has_llc = 1, \
> .has_rc6 = 1, \
> @@ -389,7 +389,7 @@ static const struct intel_device_info intel_valleyview_info = {
> .ppgtt = INTEL_PPGTT_FULL,
> .has_snoop = true,
> .has_coherent_ggtt = false,
> - .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> + .engine_mask = RENDER_RING | BSD_RING | BLT_RING,
> .display_mmio_offset = VLV_DISPLAY_BASE,
> GEN_DEFAULT_PAGE_SIZES,
> GEN_DEFAULT_PIPEOFFSETS,
> @@ -398,7 +398,7 @@ static const struct intel_device_info intel_valleyview_info = {
>
> #define G75_FEATURES \
> GEN7_FEATURES, \
> - .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
> + .engine_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
> .display.has_ddi = 1, \
> .has_fpga_dbg = 1, \
> .display.has_psr = 1, \
> @@ -462,7 +462,8 @@ static const struct intel_device_info intel_broadwell_rsvd_info = {
> static const struct intel_device_info intel_broadwell_gt3_info = {
> BDW_PLATFORM,
> .gt = 3,
> - .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
> + .engine_mask =
> + RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
> };
>
> static const struct intel_device_info intel_cherryview_info = {
> @@ -471,7 +472,7 @@ static const struct intel_device_info intel_cherryview_info = {
> .num_pipes = 3,
> .display.has_hotplug = 1,
> .is_lp = 1,
> - .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> + .engine_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> .has_64bit_reloc = 1,
> .has_runtime_pm = 1,
> .has_rc6 = 1,
> @@ -521,7 +522,8 @@ static const struct intel_device_info intel_skylake_gt2_info = {
>
> #define SKL_GT3_PLUS_PLATFORM \
> SKL_PLATFORM, \
> - .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
> + .engine_mask = \
> + RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
>
>
> static const struct intel_device_info intel_skylake_gt3_info = {
> @@ -538,7 +540,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
> GEN(9), \
> .is_lp = 1, \
> .display.has_hotplug = 1, \
> - .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
> + .engine_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
> .num_pipes = 3, \
> .has_64bit_reloc = 1, \
> .display.has_ddi = 1, \
> @@ -592,7 +594,8 @@ static const struct intel_device_info intel_kabylake_gt2_info = {
> static const struct intel_device_info intel_kabylake_gt3_info = {
> KBL_PLATFORM,
> .gt = 3,
> - .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
> + .engine_mask =
> + RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
> };
>
> #define CFL_PLATFORM \
> @@ -612,7 +615,8 @@ static const struct intel_device_info intel_coffeelake_gt2_info = {
> static const struct intel_device_info intel_coffeelake_gt3_info = {
> CFL_PLATFORM,
> .gt = 3,
> - .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
> + .engine_mask =
> + RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
> };
>
> #define GEN10_FEATURES \
> @@ -655,7 +659,8 @@ static const struct intel_device_info intel_icelake_11_info = {
> GEN11_FEATURES,
> PLATFORM(INTEL_ICELAKE),
> .is_alpha_support = 1,
> - .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
> + .engine_mask =
> + RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
> };
>
> #undef GEN
> diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
> index 55d6123dbba4..fc5c5a7e4dfb 100644
> --- a/drivers/gpu/drm/i915/i915_reset.c
> +++ b/drivers/gpu/drm/i915/i915_reset.c
> @@ -692,7 +692,7 @@ static int gt_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
> return err;
>
> for_each_engine(engine, i915, id)
> - intel_engine_reset(engine, stalled_mask & ENGINE_MASK(id));
> + intel_engine_reset(engine, stalled_mask & engine->mask);
>
> i915_gem_restore_fences(i915);
>
> @@ -1057,7 +1057,7 @@ void i915_reset(struct drm_i915_private *i915,
> static inline int intel_gt_reset_engine(struct drm_i915_private *i915,
> struct intel_engine_cs *engine)
> {
> - return intel_gpu_reset(i915, intel_engine_flag(engine));
> + return intel_gpu_reset(i915, engine->mask);
> }
>
> /**
> @@ -1241,7 +1241,7 @@ void i915_handle_error(struct drm_i915_private *i915,
> */
> wakeref = intel_runtime_pm_get(i915);
>
> - engine_mask &= INTEL_INFO(i915)->ring_mask;
> + engine_mask &= INTEL_INFO(i915)->engine_mask;
>
> if (flags & I915_ERROR_CAPTURE) {
> i915_capture_error_state(i915, engine_mask, msg);
> @@ -1260,7 +1260,7 @@ void i915_handle_error(struct drm_i915_private *i915,
> continue;
>
> if (i915_reset_engine(engine, msg) == 0)
> - engine_mask &= ~intel_engine_flag(engine);
> + engine_mask &= ~engine->mask;
>
> clear_bit(I915_RESET_ENGINE + engine->id,
> &error->flags);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 855a5074ad77..6283506e89b5 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -738,7 +738,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> runtime->num_scalers[PIPE_C] = 1;
> }
>
> - BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t));
> + BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
>
> if (IS_GEN(dev_priv, 11))
> for_each_pipe(dev_priv, pipe)
> @@ -887,7 +887,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> continue;
>
> if (!(BIT(i) & RUNTIME_INFO(dev_priv)->vdbox_enable)) {
> - info->ring_mask &= ~ENGINE_MASK(_VCS(i));
> + info->engine_mask &= ~ENGINE_MASK(_VCS(i));
> DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
> continue;
> }
> @@ -906,7 +906,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> continue;
>
> if (!(BIT(i) & RUNTIME_INFO(dev_priv)->vebox_enable)) {
> - info->ring_mask &= ~ENGINE_MASK(_VECS(i));
> + info->engine_mask &= ~ENGINE_MASK(_VECS(i));
> DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
> }
> }
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index e8b8661df746..047d10bdd455 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -150,14 +150,14 @@ struct sseu_dev_info {
> u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
> };
>
> -typedef u8 intel_ring_mask_t;
> +typedef u8 intel_engine_mask_t;
>
> struct intel_device_info {
> u16 gen_mask;
>
> u8 gen;
> u8 gt; /* GT number, 0 if undefined */
> - intel_ring_mask_t ring_mask; /* Rings supported by the HW */
> + intel_engine_mask_t engine_mask; /* Engines supported by the HW */
>
> enum intel_platform platform;
> u32 platform_mask;
> @@ -200,7 +200,7 @@ struct intel_runtime_info {
> u8 num_sprites[I915_MAX_PIPES];
> u8 num_scalers[I915_MAX_PIPES];
>
> - u8 num_rings;
> + u8 num_engines;
>
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 4fc7e2ac6278..8226871c7781 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -313,7 +313,10 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
> if (!engine)
> return -ENOMEM;
>
> + BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
> +
> engine->id = id;
> + engine->mask = BIT(id);
Could use ENGINE_MASK just because we can?
> engine->i915 = dev_priv;
> __sprint_engine_name(engine->name, info);
> engine->hw_id = engine->guc_id = info->hw_id;
> @@ -355,15 +358,15 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
> int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
> {
> struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
> - const unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask;
> + const unsigned int engine_mask = INTEL_INFO(dev_priv)->engine_mask;
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
> unsigned int mask = 0;
> unsigned int i;
> int err;
>
> - WARN_ON(ring_mask == 0);
> - WARN_ON(ring_mask &
> + WARN_ON(engine_mask == 0);
> + WARN_ON(engine_mask &
> GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
>
> if (i915_inject_load_failure())
> @@ -385,8 +388,8 @@ int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
> * are added to the driver by a warning and disabling the forgotten
> * engines.
> */
> - if (WARN_ON(mask != ring_mask))
> - device_info->ring_mask = mask;
> + if (WARN_ON(mask != engine_mask))
> + device_info->engine_mask = mask;
>
> /* We always presume we have at least RCS available for later probing */
> if (WARN_ON(!HAS_ENGINE(dev_priv, RCS))) {
> @@ -394,7 +397,7 @@ int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
> goto cleanup;
> }
>
> - RUNTIME_INFO(dev_priv)->num_rings = hweight32(mask);
> + RUNTIME_INFO(dev_priv)->num_engines = hweight32(mask);
>
> i915_check_and_clear_faults(dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
> index 56ba2fcbabe6..119d3326bb5e 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -1030,7 +1030,7 @@ static int guc_clients_create(struct intel_guc *guc)
> GEM_BUG_ON(guc->preempt_client);
>
> client = guc_client_alloc(dev_priv,
> - INTEL_INFO(dev_priv)->ring_mask,
> + INTEL_INFO(dev_priv)->engine_mask,
> GUC_CLIENT_PRIORITY_KMD_NORMAL,
> dev_priv->kernel_context);
> if (IS_ERR(client)) {
> @@ -1041,7 +1041,7 @@ static int guc_clients_create(struct intel_guc *guc)
>
> if (dev_priv->preempt_context) {
> client = guc_client_alloc(dev_priv,
> - INTEL_INFO(dev_priv)->ring_mask,
> + INTEL_INFO(dev_priv)->engine_mask,
> GUC_CLIENT_PRIORITY_KMD_HIGH,
> dev_priv->preempt_context);
> if (IS_ERR(client)) {
> diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
> index f1d8dfc58049..c508875d5236 100644
> --- a/drivers/gpu/drm/i915/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/intel_hangcheck.c
> @@ -120,7 +120,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
> */
> tmp = I915_READ_CTL(engine);
> if (tmp & RING_WAIT) {
> - i915_handle_error(dev_priv, BIT(engine->id), 0,
> + i915_handle_error(dev_priv, engine->mask, 0,
> "stuck wait on %s", engine->name);
> I915_WRITE_CTL(engine, tmp);
> return ENGINE_WAIT_KICK;
> @@ -282,13 +282,13 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
> hangcheck_store_sample(engine, &hc);
>
> if (hc.stalled) {
> - hung |= intel_engine_flag(engine);
> + hung |= engine->mask;
> if (hc.action != ENGINE_DEAD)
> - stuck |= intel_engine_flag(engine);
> + stuck |= engine->mask;
> }
>
> if (hc.wedged)
> - wedged |= intel_engine_flag(engine);
> + wedged |= engine->mask;
> }
>
> if (GEM_SHOW_DEBUG() && (hung | stuck)) {
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 1b96b0960adc..e78594ecba6f 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1692,8 +1692,8 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
> struct drm_i915_private *i915 = rq->i915;
> struct intel_engine_cs *engine = rq->engine;
> enum intel_engine_id id;
> - const int num_rings =
> - IS_HSW_GT1(i915) ? RUNTIME_INFO(i915)->num_rings - 1 : 0;
> + const int num_engines =
> + IS_HSW_GT1(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0;
> bool force_restore = false;
> int len;
> u32 *cs;
> @@ -1707,7 +1707,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
>
> len = 4;
> if (IS_GEN(i915, 7))
> - len += 2 + (num_rings ? 4*num_rings + 6 : 0);
> + len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
> if (flags & MI_FORCE_RESTORE) {
> GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
> flags &= ~MI_FORCE_RESTORE;
> @@ -1722,10 +1722,10 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
> /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
> if (IS_GEN(i915, 7)) {
> *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> - if (num_rings) {
> + if (num_engines) {
> struct intel_engine_cs *signaller;
>
> - *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
> + *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
> for_each_engine(signaller, i915, id) {
> if (signaller == engine)
> continue;
> @@ -1768,11 +1768,11 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
> *cs++ = MI_NOOP;
>
> if (IS_GEN(i915, 7)) {
> - if (num_rings) {
> + if (num_engines) {
> struct intel_engine_cs *signaller;
> i915_reg_t last_reg = {}; /* keep gcc quiet */
>
> - *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
> + *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
> for_each_engine(signaller, i915, id) {
> if (signaller == engine)
> continue;
> @@ -1859,8 +1859,8 @@ static int switch_context(struct i915_request *rq)
> goto err;
> } while (--loops);
>
> - if (intel_engine_flag(engine) & ppgtt->pd_dirty_rings) {
> - unwind_mm = intel_engine_flag(engine);
> + if (ppgtt->pd_dirty_rings & engine->mask) {
> + unwind_mm = engine->mask;
> ppgtt->pd_dirty_rings &= ~unwind_mm;
> hw_flags = MI_FORCE_RESTORE;
> }
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 2e7264119ec4..850ad892836c 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -10,12 +10,12 @@
> #include <linux/seqlock.h>
>
> #include "i915_gem_batch_pool.h"
> -
> -#include "i915_reg.h"
> #include "i915_pmu.h"
> +#include "i915_reg.h"
> #include "i915_request.h"
> #include "i915_selftest.h"
> #include "i915_timeline.h"
> +#include "intel_device_info.h"
> #include "intel_gpu_commands.h"
> #include "intel_workarounds.h"
>
> @@ -334,6 +334,7 @@ struct intel_engine_cs {
> enum intel_engine_id id;
> unsigned int hw_id;
> unsigned int guc_id;
> + intel_engine_mask_t mask;
>
> u8 uabi_id;
> u8 uabi_class;
> @@ -668,12 +669,6 @@ execlists_port_complete(struct intel_engine_execlists * const execlists,
> return port;
> }
>
> -static inline unsigned int
> -intel_engine_flag(const struct intel_engine_cs *engine)
> -{
> - return BIT(engine->id);
> -}
> -
> static inline u32
> intel_read_status_page(const struct intel_engine_cs *engine, int reg)
> {
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> index c7ea3535264a..1c608b60c55c 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> @@ -556,7 +556,7 @@ static int igt_ctx_exec(void *arg)
> ncontexts++;
> }
> pr_info("Submitted %lu contexts (across %u engines), filling %lu dwords\n",
> - ncontexts, RUNTIME_INFO(i915)->num_rings, ndwords);
> + ncontexts, RUNTIME_INFO(i915)->num_engines, ndwords);
>
> dw = 0;
> list_for_each_entry(obj, &objects, st_link) {
> @@ -1126,7 +1126,7 @@ static int igt_ctx_readonly(void *arg)
> }
> }
> pr_info("Submitted %lu dwords (across %u engines)\n",
> - ndwords, RUNTIME_INFO(i915)->num_rings);
> + ndwords, RUNTIME_INFO(i915)->num_engines);
>
> dw = 0;
> list_for_each_entry(obj, &objects, st_link) {
> @@ -1459,7 +1459,7 @@ static int igt_vm_isolation(void *arg)
> count += this;
> }
> pr_info("Checked %lu scratch offsets across %d engines\n",
> - count, RUNTIME_INFO(i915)->num_rings);
> + count, RUNTIME_INFO(i915)->num_engines);
>
> out_rpm:
> intel_runtime_pm_put(i915, wakeref);
> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
> index 7e1b65b8eb19..29875c28a544 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_request.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_request.c
> @@ -1216,7 +1216,7 @@ static int live_breadcrumbs_smoketest(void *arg)
> num_fences += atomic_long_read(&t[id].num_fences);
> }
> pr_info("Completed %lu waits for %lu fences across %d engines and %d cpus\n",
> - num_waits, num_fences, RUNTIME_INFO(i915)->num_rings, ncpus);
> + num_waits, num_fences, RUNTIME_INFO(i915)->num_engines, ncpus);
>
> mutex_lock(&i915->drm.struct_mutex);
> ret = igt_live_test_end(&live) ?: ret;
> diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c b/drivers/gpu/drm/i915/selftests/intel_guc.c
> index c5e0a0e98fcb..b05a21eaa8f4 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_guc.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_guc.c
> @@ -111,7 +111,7 @@ static int validate_client(struct intel_guc_client *client,
> dev_priv->preempt_context : dev_priv->kernel_context;
>
> if (client->owner != ctx_owner ||
> - client->engines != INTEL_INFO(dev_priv)->ring_mask ||
> + client->engines != INTEL_INFO(dev_priv)->engine_mask ||
> client->priority != client_priority ||
> client->doorbell_id == GUC_DOORBELL_INVALID)
> return -EINVAL;
> @@ -261,7 +261,7 @@ static int igt_guc_doorbells(void *arg)
>
> for (i = 0; i < ATTEMPTS; i++) {
> clients[i] = guc_client_alloc(dev_priv,
> - INTEL_INFO(dev_priv)->ring_mask,
> + INTEL_INFO(dev_priv)->engine_mask,
> i % GUC_CLIENT_PRIORITY_NUM,
> dev_priv->kernel_context);
>
> diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> index 12e047328ab8..5624a238244e 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> @@ -1358,7 +1358,7 @@ static int __igt_reset_evict_vma(struct drm_i915_private *i915,
>
> out_reset:
> igt_global_reset_lock(i915);
> - fake_hangcheck(rq->i915, intel_engine_flag(rq->engine));
> + fake_hangcheck(rq->i915, rq->engine->mask);
> igt_global_reset_unlock(i915);
>
> if (tsk) {
> @@ -1643,7 +1643,7 @@ static int igt_handle_error(void *arg)
> /* Temporarily disable error capture */
> error = xchg(&i915->gpu_error.first_error, (void *)-1);
>
> - i915_handle_error(i915, ENGINE_MASK(engine->id), 0, NULL);
> + i915_handle_error(i915, engine->mask, 0, NULL);
>
> xchg(&i915->gpu_error.first_error, error);
>
> diff --git a/drivers/gpu/drm/i915/selftests/intel_lrc.c b/drivers/gpu/drm/i915/selftests/intel_lrc.c
> index 0677038a5466..565e949a4722 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_lrc.c
> @@ -929,7 +929,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags)
>
> pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n",
> count, flags,
> - RUNTIME_INFO(smoke->i915)->num_rings, smoke->ncontext);
> + RUNTIME_INFO(smoke->i915)->num_engines, smoke->ncontext);
> return 0;
> }
>
> @@ -957,7 +957,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags)
>
> pr_info("Submitted %lu random:%x requests across %d engines and %d contexts\n",
> count, flags,
> - RUNTIME_INFO(smoke->i915)->num_rings, smoke->ncontext);
> + RUNTIME_INFO(smoke->i915)->num_engines, smoke->ncontext);
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
> index 33b3ced83fde..79a836d21abf 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
> @@ -222,7 +222,7 @@ static int check_whitelist(struct i915_gem_context *ctx,
>
> static int do_device_reset(struct intel_engine_cs *engine)
> {
> - i915_reset(engine->i915, ENGINE_MASK(engine->id), "live_workarounds");
> + i915_reset(engine->i915, engine->mask, "live_workarounds");
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c b/drivers/gpu/drm/i915/selftests/mock_engine.c
> index ec1ae948954c..c2c954f64226 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_engine.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_engine.c
> @@ -223,6 +223,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
> engine->base.i915 = i915;
> snprintf(engine->base.name, sizeof(engine->base.name), "%s", name);
> engine->base.id = id;
> + engine->base.mask = BIT(id);
> engine->base.status_page.addr = (void *)(engine + 1);
>
> engine->base.context_pin = mock_context_pin;
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index c27616efc4f8..8581cf5e0e8c 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -206,7 +206,7 @@ struct drm_i915_private *mock_gem_device(void)
>
> mock_init_ggtt(i915, &i915->ggtt);
>
> - mkwrite_device_info(i915)->ring_mask = BIT(0);
> + mkwrite_device_info(i915)->engine_mask = BIT(0);
> i915->kernel_context = mock_context(i915, NULL);
> if (!i915->kernel_context)
> goto err_unlock;
>
Looks good. I would consider making the patch bigger since one merge
conflict is better than two.
Regards,
Tvrtko
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