[Intel-gfx] [PATCH i-g-t v4 0/1] gem_ctx_isolation.c - Gen11 enabling for context isolation test

[Dale B Stimson]

V4:

I have tested these changes on both SKL and ICL with no regressions
detected.

I will note that both SKL and ICL seem to currently have (at least for
my environment) suspend/resume issues which occur with or without these
changes (and also for gem_exec_suspend).  Therefore, the S3/S4 tests
were not done.

Testing on ICL shows that Gen11 requires BB_OFFSET .ignore_bits =
0x7 instead of 0x4.  I presume that the preferred way to do this is to
change the existing table entry for BB_OFFSET instead of splitting it
into separate entries for GEN8-10 and GEN11.

For those registers that are force_nonpriv for some Gen levels and
not for others, I have chosen to show the two states as separate table
entries to make this clear.  In particular, this applies as shown below.
Any objections to doing it that way?

+       { "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 },
+       { "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true },
+       { "HDC_CHICKEN1", GEN_RANGE(10, 10), RCS0, 0x7304, .masked = true },
+
        /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
-       { "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
+       { "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 },
        { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
-       { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
+       { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true },

Dale B Stimson (1):
  gem_ctx_isolation.c - Gen11 enabling for context isolation test

 tests/i915/gem_ctx_isolation.c | 47 +++++++++++++++++++++++++---------
 1 file changed, 35 insertions(+), 12 deletions(-)

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2.21.0