[Intel-gfx] [PATCH 4/4] drm/i915/gtt: Mark ALL_ENGINES as dirty on ppGTT modification

[Mika Kuoppala]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> Small simplification to set all bits in the dirty mask rather than
> lookup the exact mask of populated engines. The bits for the engines
> that do not exist are unused and so can safely set and then ignored.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.auld at intel.com>
> Cc: Mika Kuoppala <mika.kuoppala at intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index db5364df0803..d31356264ee2 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -782,14 +782,15 @@ static void gen8_initialize_pml4(struct i915_address_space *vm,
>  	fill_px(vm, pml4, vm->scratch_pte);
>  }
>  
> -/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
> +/*
> + * PDE TLBs are a pain to invalidate on GEN8+. When we modify
>   * the page table structures, we mark them dirty so that
>   * context switching/execlist queuing code takes extra steps
>   * to ensure that tlbs are flushed.
>   */
>  static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
>  {
> -	ppgtt->pd_dirty_engines = INTEL_INFO(ppgtt->vm.i915)->engine_mask;
> +	ppgtt->pd_dirty_engines = ALL_ENGINES;
>  }
>  
>  /* Removes entries from a single page table, releasing it if it's empty.
> -- 
> 2.20.1
>
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