[Intel-gfx] [PATCH 1/2] drm/i915/dp: deconflate PPS unlock from divisor register

[Rodrigo Vivi]

On Tue, Mar 05, 2019 at 03:52:14PM +0200, Jani Nikula wrote:
> PPS locking is a thing on pre-DDI, up to and including CPT and PPT.
> 
> The PPS divisor register exists up to gen 9 BC, replaced by a field in
> the control register starting from gen 9 LP, i.e. BXT, GLK, and CNP on.
> 
> Commit b0a08bec9631 ("drm/i915/bxt: eDP Panel Power sequencing") stopped
> using the divisor register, but inadvertently conflated the PPS unlock
> in the change. No longer doing the unlocking was the right thing to do,
> however we should've stopped already at LPT (or DDI platforms).
> 
> Deconflate the two.
> 
> Arguably this could be moved away from here altogether, but this is the
> minimally intrusive change for now.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e1a051c0fbfe..e0f421e76305 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -6425,15 +6425,16 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
>  
>  	intel_pps_get_registers(intel_dp, &regs);
>  
> -	/* Workaround: Need to write PP_CONTROL with the unlock key as
> -	 * the very first thing. */
>  	pp_ctl = ironlake_get_pp_control(intel_dp);
>  
> +	/* Ensure PPS is unlocked */
> +	if (!HAS_DDI(dev_priv))
> +		I915_WRITE(regs.pp_ctrl, pp_ctl);
> +
>  	pp_on = I915_READ(regs.pp_on);
>  	pp_off = I915_READ(regs.pp_off);
>  	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
>  	    !HAS_PCH_ICP(dev_priv)) {
> -		I915_WRITE(regs.pp_ctrl, pp_ctl);
>  		pp_div = I915_READ(regs.pp_div);
>  	}
>  
> -- 
> 2.20.1
>