[Intel-gfx] [PATCH v2] drm/i915/icl: Fix CRC mismatch error for DP link layer compliance

[Maarten Lankhorst]

Op 08-03-2019 om 12:39 schreef Saarinen, Jani:
> Ping, ok to merge? 
Could we have an icl shards run on this before merging?
>> -----Original Message-----
>> From: Intel-gfx [mailto:intel-gfx-bounces at lists.freedesktop.org] On Behalf Of
>> Kahola, Mika
>> Sent: torstai 7. maaliskuuta 2019 9.52
>> To: intel-gfx at lists.freedesktop.org; Swarup, Aditya <aditya.swarup at intel.com>
>> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/icl: Fix CRC mismatch error for DP link
>> layer compliance
>>
>> The patch looks ok to me.
>>
>> On Wed, 2019-03-06 at 18:14 -0800, Aditya Swarup wrote:
>>> Setting the pixel rounding bit to 1 in PIPE_CHICKEN register allows to
>>> passthrough FB pixels unmodified across pipe. This fixes the failures
>>> for DP link layer compliance tests 4.4.1.1, 4.4.1.2 & 4.4.1.3.
>>> (Lineage #1605353570)
>>>
>>> v2: This is also needed to fix failing IGT test case kms_cursor_crc on
>>> ICL.(Mika Kahola) Make macros consistent with i915_reg.h
>>> comments.(Jani Nikula)
>>>
>>> Cc: Clint Taylor <clinton.a.taylor at intel.com>
>>> Cc: Mika Kahola <mika.kahola at intel.com>
>>> Cc: Jani Nikula <jani.nikula at linux.intel.com>
>> Reviewed-by: Mika Kahola <mika.kahola at intel.com>
>>
>>> Signed-off-by: Aditya Swarup <aditya.swarup at intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/i915_reg.h      | 13 +++++++------
>>>  drivers/gpu/drm/i915/intel_display.c |  8 +++++++-
>>>  2 files changed, 14 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>> b/drivers/gpu/drm/i915/i915_reg.h index c9b868347481..cf15a9a97d74
>>> 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -7659,12 +7659,13 @@ enum {
>>>  #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1 << 2)
>>>
>>>  /*GEN11 chicken */
>>> -#define _PIPEA_CHICKEN			0x70038
>>> -#define _PIPEB_CHICKEN			0x71038
>>> -#define _PIPEC_CHICKEN			0x72038
>>> -#define  PER_PIXEL_ALPHA_BYPASS_EN	(1 << 7)
>>> -#define PIPE_CHICKEN(pipe)		_MMIO_PIPE(pipe,
>>> _PIPEA_CHICKEN,\
>>> -						   _PIPEB_CHICKEN)
>>> +#define _PIPEA_CHICKEN				0x70038
>>> +#define _PIPEB_CHICKEN				0x71038
>>> +#define _PIPEC_CHICKEN				0x72038
>>> +#define PIPE_CHICKEN(pipe)			_MMIO_PIPE(pipe,
>>> _PIPEA_CHICKEN,\
>>> +							   _PIPEB_CHICK
>>> EN)
>>> +#define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
>>> +#define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
>>>
>>>  /* PCH */
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>>> b/drivers/gpu/drm/i915/intel_display.c
>>> index d852cb282060..92be3476fef1 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -3970,7 +3970,13 @@ static void icl_set_pipe_chicken(struct
>>> intel_crtc *crtc)
>>>  	 * and rounding for per-pixel values 00 and 0xff
>>>  	 */
>>>  	tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
>>> -
>>> +	/*
>>> +	 * Display WA # 1605353570: icl
>>> +	 * Set the pixel rounding bit to 1 for allowing
>>> +	 * passthrough of Frame buffer pixels unmodified
>>> +	 * across pipe
>>> +	 */
>>> +	tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
>>>  	I915_WRITE(PIPE_CHICKEN(pipe), tmp);  }
>>>
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