[Intel-gfx] [PATCH v3 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR

[Souza, Jose]

On Mon, 2019-03-11 at 16:34 -0700, Rodrigo Vivi wrote:
> On Tue, Mar 05, 2019 at 03:47:34PM -0800, José Roberto de Souza
> wrote:
> > TPS4 support was added to PSR because HBR3/PSR spec was not closed
> > when ICL was freezed so if HBR3 was supported by PSR, ICL would
> > already be ready but it was not added to spec so lets always
> > disable TPS4.
> > 
> > v3: Missed ";" SPANK SPANK SPANK!!!
> > 
> > BSpec: 17524
> > 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  | 2 ++
> >  drivers/gpu/drm/i915/intel_psr.c | 3 +++
> >  2 files changed, 5 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 16ce9c609c65..a7697909e0c9 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4205,6 +4205,8 @@ enum {
> >  #define   EDP_PSR_TP2_TP3_TIME_100us		(1 << 8)
> >  #define   EDP_PSR_TP2_TP3_TIME_2500us		(2 << 8)
> >  #define   EDP_PSR_TP2_TP3_TIME_0us		(3 << 8)
> > +#define   EDP_PSR_TP4_TIME_SHIFT		(6) /* ICL+ */
> > +#define   EDP_PSR_TP4_TIME_0US			(3 <<
> > EDP_PSR_TP4_TIME_SHIFT) /* ICL+ */
> 
> could we please leave this as the rest of the reg and use (3 << 6)
> imo easier to read because the rest of reg was already there

Sure, I will change to (3 << 6)

> 
> >  #define   EDP_PSR_TP1_TIME_500us		(0 << 4)
> >  #define   EDP_PSR_TP1_TIME_100us		(1 << 4)
> >  #define   EDP_PSR_TP1_TIME_2500us		(2 << 4)
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 2fa2f4c9c935..c70d735f5b93 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -442,6 +442,9 @@ static u32 psr1_tps_regs_val_get(struct
> > intel_dp *intel_dp)
> >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >  	u32 val = 0;
> >  
> > +	if (INTEL_GEN(dev_priv) >= 11)
> > +		val |= EDP_PSR_TP4_TIME_0US;
> > +
> >  	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> >  		val |= EDP_PSR_TP1_TIME_0us;
> >  	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
> > -- 
> > 2.21.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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