[Intel-gfx] [PATCH 1/2] drm/i915/cml: Add CML PCI IDS

[Rodrigo Vivi]

On Thu, Mar 14, 2019 at 11:29:17AM -0700, Anusha wrote:
> From: Anusha Srivatsa <anusha.srivatsa at intel.com>
> 
> Comet Lake is a Intel Processor containing Gen9
> Intel HD Graphics. This patch adds the initial set of
> PCI IDs. Comet Lake comes off of Coffee Lake - adding
> the IDs to Coffee Lake ID list.
> 
> More support and features will be in the patches that follow.
> 
> v2: Split IDs according to GT. (Rodrigo)
> 
> v3: Update IDs.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_pci.c |  2 ++
>  include/drm/i915_pciids.h       | 31 ++++++++++++++++++++++++++++++-
>  2 files changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 3cf697e8f1fa..b5baa7a200d0 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -789,6 +789,8 @@ static const struct pci_device_id pciidlist[] = {
>  	INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
>  	INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
>  	INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
> +	INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
> +	INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
>  	INTEL_CNL_IDS(&intel_cannonlake_info),
>  	INTEL_ICL_11_IDS(&intel_icelake_11_info),
>  	{0, 0, 0}
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index d200000feeaa..c97b9774d458 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -373,6 +373,34 @@
>  #define INTEL_AML_CFL_GT2_IDS(info) \
>  	INTEL_VGA_DEVICE(0x87CA, info)
>  
> +/* CML GT1 */
> +#define INTEL_CML_GT1_IDS(info)	\
> +	INTEL_VGA_DEVICE(0x9B21, info), \
> +	INTEL_VGA_DEVICE(0x9BAA, info), \
> +	INTEL_VGA_DEVICE(0x9BAB, info), \
> +	INTEL_VGA_DEVICE(0x9BAC, info), \
> +	INTEL_VGA_DEVICE(0x9BA0, info), \
> +	INTEL_VGA_DEVICE(0x9BA5, info), \
> +	INTEL_VGA_DEVICE(0x9BA8, info), \
> +	INTEL_VGA_DEVICE(0x9BA4, info), \
> +	INTEL_VGA_DEVICE(0x9BA2, info)
> +
> +/* CML GT2 */
> +#define INTEL_CML_GT2_IDS(info)	\
> +	INTEL_VGA_DEVICE(0x9B41, info), \
> +	INTEL_VGA_DEVICE(0x9BCA, info), \
> +	INTEL_VGA_DEVICE(0x9BCB, info), \
> +	INTEL_VGA_DEVICE(0x9BCC, info), \
> +	INTEL_VGA_DEVICE(0x9BC0, info), \
> +	INTEL_VGA_DEVICE(0x9BC5, info), \
> +	INTEL_VGA_DEVICE(0x9BC8, info), \
> +	INTEL_VGA_DEVICE(0x9BC4, info), \
> +	INTEL_VGA_DEVICE(0x9BC2, info)
> +
> +#define INTEL_CML_IDS(info) \
> +	INTEL_CML_GT1_IDS(info), \
> +	INTEL_CML_GT2_IDS(info)
> +

I think this block is not needed and doesn't match
what is in place for WHL.

with this removed:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

>  #define INTEL_KBL_IDS(info) \
>  	INTEL_KBL_GT1_IDS(info), \
>  	INTEL_KBL_GT2_IDS(info), \
> @@ -436,7 +464,8 @@
>  	INTEL_WHL_U_GT1_IDS(info), \
>  	INTEL_WHL_U_GT2_IDS(info), \
>  	INTEL_WHL_U_GT3_IDS(info), \
> -	INTEL_AML_CFL_GT2_IDS(info)
> +	INTEL_AML_CFL_GT2_IDS(info), \
> +	INTEL_CML_IDS(info)
>  
>  /* CNL */
>  #define INTEL_CNL_IDS(info) \
> -- 
> 2.21.0
>