[Intel-gfx] [PATCH 3/9] drm/i915/ehl: ehl and icl are both gen11

[Lucas De Marchi]

On Wed, Mar 13, 2019 at 02:11:38PM -0700, Rodrigo Vivi wrote:
>From: Bob Paauwe <bob.j.paauwe at intel.com>
>
>Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
>so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
>
>Signed-off-by: Bob Paauwe <bob.j.paauwe at intel.com>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/intel_pm.c          | 2 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c  | 4 ++--
> drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++----
> 3 files changed, 7 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index d73b13ca57a0..61c581e33fe3 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -9468,7 +9468,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>  */
> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> {
>-	if (IS_ICELAKE(dev_priv))
>+	if (IS_GEN(dev_priv, 11))
> 		dev_priv->display.init_clock_gating = icl_init_clock_gating;
> 	else if (IS_CANNONLAKE(dev_priv))
> 		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
>diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
>index 676a89bb8194..1f063c761f35 100644
>--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>@@ -3442,7 +3442,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> 	 * The enabling order will be from lower to higher indexed wells,
> 	 * the disabling order is reversed.
> 	 */
>-	if (IS_ICELAKE(dev_priv)) {
>+	if (IS_GEN(dev_priv, 11)) {
> 		err = set_power_wells(power_domains, icl_power_wells);
> 	} else if (IS_CANNONLAKE(dev_priv)) {
> 		err = set_power_wells(power_domains, cnl_power_wells);
>@@ -4203,7 +4203,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
> 		intel_power_domains_verify_state(i915);
> 	}
>
>-	if (IS_ICELAKE(i915))
>+	if (IS_GEN(i915, 11))
> 		icl_display_core_uninit(i915);
> 	else if (IS_CANNONLAKE(i915))
> 		cnl_display_core_uninit(i915);
>diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
>index 283e9a4ef3ca..2128cb6cf8c8 100644
>--- a/drivers/gpu/drm/i915/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/intel_workarounds.c
>@@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
>
> 	wa_init_start(wal, "context");
>
>-	if (IS_ICELAKE(i915))
>+	if (IS_GEN(i915, 11))
> 		icl_ctx_workarounds_init(engine);
> 	else if (IS_CANNONLAKE(i915))
> 		cnl_ctx_workarounds_init(engine);
>@@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> static void
> gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
>-	if (IS_ICELAKE(i915))
>+	if (IS_GEN(i915, 11))
> 		icl_gt_workarounds_init(i915, wal);
> 	else if (IS_CANNONLAKE(i915))
> 		cnl_gt_workarounds_init(i915, wal);
>@@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>
> 	wa_init_start(w, "whitelist");
>
>-	if (IS_ICELAKE(i915))
>+	if (IS_GEN(i915, 11))
> 		icl_whitelist_build(w);
> 	else if (IS_CANNONLAKE(i915))
> 		cnl_whitelist_build(w);
>@@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> {
> 	struct drm_i915_private *i915 = engine->i915;
>
>-	if (IS_ICELAKE(i915)) {
>+	if (IS_GEN(i915, 11)) {
> 		/* This is not an Wa. Enable for better image quality */
> 		wa_masked_en(wal,
> 			     _3D_CHICKEN3,
>-- 
>2.20.1
>
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