[Intel-gfx] [PATCH 3/3] drm/i915: Introduce concept of a sub-platform
Tvrtko Ursulin
tvrtko.ursulin at linux.intel.com
Mon Mar 18 09:52:58 UTC 2019
From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Concept of a sub-platform already exist in our code (like ULX and ULT
platform variants and similar),implemented via the macros which check a
list of device ids to determine a match.
With this patch we consolidate device ids checking into a single function
called during early driver load.
A few low bits in the platform mask are reserved for sub-platform
identification and defined as a per-platform namespace.
At the same time it future proofs the platform_mask handling by preparing
the code for easy extending, and tidies the very verbose WARN strings
generated when IS_PLATFORM macros are embedded into a WARN type
statements.
v2: Fixed IS_SUBPLATFORM. Updated commit msg.
v3: Chris was right, there is an ordering problem.
v4:
* Catch-up with new sub-platforms.
* Rebase for RUNTIME_INFO.
* Drop subplatform mask union tricks and convert platform_mask to an
array for extensibility.
v5:
* Fix subplatform check.
* Protect against forgetting to expand subplatform bits.
* Remove platform enum tallying.
* Add subplatform to error state. (Chris)
* Drop macros and just use static inlines.
* Remove redundant IRONLAKE_M. (Ville)
v6:
* Split out Ironlake change.
* Optimize subplatform check.
* Use __always_inline. (Lucas)
* Add platform_mask comment. (Paulo)
* Pass stored runtime info in error capture. (Chris)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Suggested-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula at intel.com>
Cc: Lucas De Marchi <lucas.demarchi at intel.com>
Cc: Jose Souza <jose.souza at intel.com>
Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
The main question here is whether the subplatform concept is an
improvement with regards to cleaning up where we sprinkle device ids
both in the source and during runtime checks.
Size wise it is a small reduction and an improvement in WARN string
readability where IS_PLATFORM checks are used.
tursulin at tursulin-mobl2:~/build/drm-intel$ size i915.ko.*
text data bss dec hex filename
1867088 43651 7392 1918131 1d44b3 i915.ko.0
1865851 43651 7392 1916894 1d3fde i915.ko.1
* Expanding the platform_mask array does not increase the size.
tursulin at tursulin-mobl2:~/build/drm-intel$ scripts/bloat-o-meter i915.ko.0 i915.ko.1
add/remove: 3/2 grow/shrink: 79/122 up/down: 1271/-1643 (-372)
Function old new delta
intel_device_info_subplatform_init - 412 +412
intel_get_gpu_reset - 99 +99
intel_atomic_check 4676 4744 +68
intel_crtc_max_vblank_count.isra - 64 +64
intel_power_domains_suspend 588 625 +37
intel_ddi_get_buf_trans_dp 150 187 +37
intel_sdvo_get_config 916 946 +30
intel_power_sequencer_reset 235 263 +28
__err_print_to_sgl 4075 4100 +25
i9xx_plane_check 395 417 +22
i915_getparam_ioctl 600 622 +22
gen5_gt_irq_postinstall 284 306 +22
gt_init_workarounds 893 913 +20
intel_crtc_verify_crc_source 240 258 +18
ilk_load_csc_matrix 372 389 +17
intel_hdmi_compute_config 1873 1888 +15
intel_pps_get_registers 383 397 +14
skl_write_plane_wm 482 495 +13
ilk_wm_get_hw_state 1065 1077 +12
intel_dp_init_connector 3506 3517 +11
snb_gt_irq_handler 278 288 +10
intel_tile_width_bytes 277 287 +10
ilk_compute_pipe_wm 1050 1060 +10
wm_latency_show 223 232 +9
skl_write_cursor_wm 332 341 +9
skl_plane_wm_equals 245 254 +9
skl_pipe_wm_get_hw_state 495 504 +9
ivybridge_parity_work 815 824 +9
intel_sdvo_pre_enable 2129 2138 +9
intel_print_wm_latency 210 219 +9
intel_plane_atomic_calc_changes 1777 1786 +9
ilk_compute_intermediate_wm 508 517 +9
i9xx_update_wm 1142 1151 +9
i9xx_get_initial_plane_config 972 981 +9
i915_setup_sysfs 441 450 +9
intel_rc6_residency_ns 637 644 +7
intel_psr_init 301 308 +7
intel_opregion_setup 1568 1575 +7
intel_sdvo_dvi_init 522 528 +6
intel_init_cdclk_hooks 586 592 +6
intel_hpll_vco 175 181 +6
intel_has_gpu_reset 33 39 +6
get_new_crc_ctl_reg 621 627 +6
skl_allocate_pipe_ddb 2406 2411 +5
intel_overlay_put_image_ioctl 4833 4838 +5
i9xx_get_pipe_config 1633 1638 +5
vlv_dsi_init 1269 1273 +4
intel_enable_dp 831 835 +4
i915_ggtt_init_hw 306 310 +4
i915_gem_load_init_fences 264 268 +4
intel_set_memory_cxsr 102 105 +3
intel_psr_enable_locked 912 915 +3
intel_plane_compute_aligned_offset 173 176 +3
intel_init_display_hooks 668 671 +3
intel_engine_can_store_dword 48 51 +3
intel_disable_gt_powersave 897 900 +3
igt_partial_tiling 928 931 +3
i915_gem_set_tiling_ioctl 879 882 +3
i915_driver_load 5593 5596 +3
fence_write 577 580 +3
wm_latency_write.isra 335 337 +2
set_data 116 118 +2
set_clock 110 112 +2
intel_update_rawclk 256 258 +2
intel_runtime_suspend 550 552 +2
intel_plane_pin_fb 178 180 +2
intel_init_audio_hooks 119 121 +2
intel_infoframe_init 323 325 +2
intel_enable_gt_powersave 6202 6204 +2
intel_device_info_runtime_init 5000 5002 +2
intel_crt_detect 2185 2187 +2
ilk_increase_wm_latency.constprop 110 112 +2
gen6_rps_idle 193 195 +2
intel_enable_pipe 697 698 +1
intel_dp_pre_emphasis_max 130 131 +1
ilk_wm_max_level 51 52 +1
icl_combo_phy_aux_power_well_enable 343 344 +1
i9xx_compute_dpll.isra.constprop 276 277 +1
i915_reset 934 935 +1
i915_drpc_info 2145 2146 +1
assert_panel_unlocked 556 557 +1
__intel_fbc_post_update 2681 2682 +1
intel_lpe_audio_init 110 109 -1
intel_irq_init 1155 1154 -1
intel_init_clock_gating_hooks 426 425 -1
intel_dp_init_panel_power_sequencer_registers 765 764 -1
capture 6084 6083 -1
intel_crt_get_modes 137 135 -2
intel_power_domains_init_hw 1308 1305 -3
intel_dp_compute_config 2959 2956 -3
intel_csr_ucode_init 548 545 -3
i9xx_check_plane_surface 416 413 -3
i915_gem_detect_bit_6_swizzle 518 515 -3
check_for_unclaimed_mmio 224 221 -3
intel_valleyview_info 112 108 -4
intel_uncore_init 1646 1642 -4
intel_surf_alignment.isra 154 150 -4
intel_sprite_plane_create 591 587 -4
intel_skylake_gt4_info 112 108 -4
intel_skylake_gt3_info 112 108 -4
intel_skylake_gt2_info 112 108 -4
intel_skylake_gt1_info 112 108 -4
intel_setup_gmbus 702 698 -4
intel_sandybridge_m_gt2_info 112 108 -4
intel_sandybridge_m_gt1_info 112 108 -4
intel_sandybridge_d_gt2_info 112 108 -4
intel_sandybridge_d_gt1_info 112 108 -4
intel_pineview_m_info 112 108 -4
intel_pineview_g_info 112 108 -4
intel_panel_init 647 643 -4
intel_kabylake_gt3_info 112 108 -4
intel_kabylake_gt2_info 112 108 -4
intel_kabylake_gt1_info 112 108 -4
intel_ivybridge_q_info 112 108 -4
intel_ivybridge_m_gt2_info 112 108 -4
intel_ivybridge_m_gt1_info 112 108 -4
intel_ivybridge_d_gt2_info 112 108 -4
intel_ivybridge_d_gt1_info 112 108 -4
intel_ironlake_m_info 112 108 -4
intel_ironlake_d_info 112 108 -4
intel_icelake_11_info 112 108 -4
intel_i965gm_info 112 108 -4
intel_i965g_info 112 108 -4
intel_i945gm_info 112 108 -4
intel_i945g_info 112 108 -4
intel_i915gm_info 112 108 -4
intel_i915g_info 112 108 -4
intel_i865g_info 112 108 -4
intel_i85x_info 112 108 -4
intel_i845g_info 112 108 -4
intel_i830_info 112 108 -4
intel_haswell_gt3_info 112 108 -4
intel_haswell_gt2_info 112 108 -4
intel_haswell_gt1_info 112 108 -4
intel_gm45_info 112 108 -4
intel_geminilake_info 112 108 -4
intel_g45_info 112 108 -4
intel_g33_info 112 108 -4
intel_dsi_get_hw_state 627 623 -4
intel_coffeelake_gt3_info 112 108 -4
intel_coffeelake_gt2_info 112 108 -4
intel_coffeelake_gt1_info 112 108 -4
intel_cherryview_info 112 108 -4
intel_cannonlake_info 112 108 -4
intel_broxton_info 112 108 -4
intel_broadwell_rsvd_info 112 108 -4
intel_broadwell_gt3_info 112 108 -4
intel_broadwell_gt2_info 112 108 -4
intel_broadwell_gt1_info 112 108 -4
intel_uncore_forcewake_for_reg 889 884 -5
intel_teardown_mchbar 210 205 -5
intel_read_wm_latency 720 715 -5
intel_engine_init_ctx_wa 1262 1257 -5
intel_engine_init_whitelist 391 385 -6
intel_dp_prepare 664 658 -6
intel_dp_encoder_reset 308 302 -6
i915_gem_init_stolen 2386 2380 -6
i915_drm_suspend_late 268 262 -6
hsw_crtc_state_ips_capable 127 121 -6
intel_power_domains_init 807 800 -7
intel_hpd_pin_default 106 99 -7
i9xx_hpd_irq_handler 245 237 -8
i915_save_state 638 630 -8
i915_rps_boost_info 843 835 -8
intel_display_print_error_state 821 812 -9
intel_color_check 1105 1096 -9
i915_ips_status 214 205 -9
i915_get_crtc_scanoutpos 580 571 -9
hsw_get_cdclk 147 138 -9
haswell_get_pipe_config 3226 3217 -9
gen9_ctx_workarounds_init 650 641 -9
intel_pipe_config_compare 5710 5700 -10
intel_crtc_atomic_check 1302 1292 -10
csr_load_work_fn 974 964 -10
i915_pm_resume_early 285 274 -11
ilk_wm_merge.isra 517 504 -13
gmbus_xfer_read 644 631 -13
intel_PLL_is_valid 206 192 -14
edp_notify_handler 221 207 -14
intel_ddi_get_buf_trans_hdmi 153 138 -15
i915_sr_status 334 319 -15
i9xx_setup_backlight 253 237 -16
ilk_program_watermarks 2096 2079 -17
intel_update_max_cdclk 779 761 -18
rcs_engine_wa_init.isra 770 751 -19
_intel_set_memory_cxsr 752 733 -19
intel_runtime_resume 574 554 -20
skl_compute_wm_levels 994 973 -21
intel_init_pm 1955 1934 -21
intel_dp_link_down.isra 675 653 -22
skl_universal_plane_create 900 876 -24
i9xx_set_pipeconf 377 350 -27
intel_dp_get_config 576 543 -33
intel_modeset_init 6040 6005 -35
intel_crtc_compute_min_cdclk 460 423 -37
intel_has_gpu_reset.part 41 - -41
intel_crtc_vblank_on 84 43 -41
intel_ddi_get_buf_trans_edp 392 349 -43
gen8_de_irq_handler 2221 2178 -43
kbl_get_buf_trans_dp 130 86 -44
intel_modeset_setup_hw_state 4466 4415 -51
intel_dsi_prepare 3710 3651 -59
gen8_de_irq_postinstall 904 826 -78
skl_get_buf_trans_dp 92 - -92
intel_gpu_reset 508 389 -119
intel_pch_type 1448 1272 -176
Total: Before=1277298, After=1276926, chg -0.03%
---
drivers/gpu/drm/i915/i915_drv.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 124 ++++++++++++++++-------
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 66 ++++++++++++
drivers/gpu/drm/i915/intel_device_info.h | 25 ++++-
6 files changed, 186 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a3b00ecc58c9..06b967937247 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -863,6 +863,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
if (i915_inject_load_failure())
return -ENODEV;
+ intel_device_info_subplatform_init(dev_priv);
+
spin_lock_init(&dev_priv->irq_lock);
spin_lock_init(&dev_priv->gpu_error.lock);
mutex_init(&dev_priv->backlight_lock);
@@ -1752,10 +1754,12 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
if (drm_debug & DRM_UT_DRIVER) {
struct drm_printer p = drm_debug_printer("i915 device info:");
- drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
+ drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
INTEL_DEVID(dev_priv),
INTEL_REVID(dev_priv),
intel_platform_name(INTEL_INFO(dev_priv)->platform),
+ intel_subplatform(RUNTIME_INFO(dev_priv),
+ INTEL_INFO(dev_priv)->platform),
INTEL_GEN(dev_priv));
intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
@@ -1798,8 +1802,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
memcpy(device_info, match_info, sizeof(*device_info));
RUNTIME_INFO(i915)->device_id = pdev->device;
- BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
- BITS_PER_TYPE(device_info->platform_mask));
BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
return i915;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2f6bc9670bdf..fd5d58abbfba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2281,7 +2281,68 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_REVID(p, since, until) \
(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
-#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
+static __always_inline unsigned int
+__platform_mask_index(const struct intel_runtime_info *info,
+ enum intel_platform p)
+{
+ const unsigned int pbits =
+ BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
+
+ /* Expand the platform_mask array if this fails. */
+ BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
+ pbits * ARRAY_SIZE(info->platform_mask));
+
+ return p / pbits;
+}
+
+static __always_inline unsigned int
+__platform_mask_bit(const struct intel_runtime_info *info,
+ enum intel_platform p)
+{
+ const unsigned int pbits =
+ BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
+
+ return p % pbits + INTEL_SUBPLATFORM_BITS;
+}
+
+static inline u32
+intel_subplatform(const struct intel_runtime_info *info,
+ enum intel_platform p)
+{
+ const unsigned int pi = __platform_mask_index(info, p);
+
+ return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
+}
+
+static __always_inline bool
+IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
+{
+ const struct intel_runtime_info *info = RUNTIME_INFO(i915);
+ const unsigned int pi = __platform_mask_index(info, p);
+ const unsigned int pb = __platform_mask_bit(info, p);
+
+ BUILD_BUG_ON(!__builtin_constant_p(p));
+
+ return info->platform_mask[pi] & BIT(pb);
+}
+
+static __always_inline bool
+IS_SUBPLATFORM(const struct drm_i915_private *i915,
+ enum intel_platform p, unsigned int s)
+{
+ const struct intel_runtime_info *info = RUNTIME_INFO(i915);
+ const unsigned int pi = __platform_mask_index(info, p);
+ const unsigned int pb = __platform_mask_bit(info, p);
+ const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
+ const u32 mask = info->platform_mask[pi];
+
+ BUILD_BUG_ON(!__builtin_constant_p(p));
+ BUILD_BUG_ON(!__builtin_constant_p(s));
+ BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
+
+ /* Shift and test on the MSB position so sign flag can be used. */
+ return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
+}
#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
@@ -2301,7 +2362,7 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
-#define IS_IRONLAKE_M(dev_priv) \
+#define IS_IRONLAKE_M(dev_priv) \
(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
@@ -2319,42 +2380,31 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
-#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
- ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
- (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
- (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
-/* ULX machines are also considered ULT. */
-#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
- (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
+#define IS_BDW_ULT(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
+#define IS_BDW_ULX(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 3)
-#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
- (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
+#define IS_HSW_ULT(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 3)
#define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 1)
/* ULX machines are also considered ULT. */
-#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
- INTEL_DEVID(dev_priv) == 0x0A1E)
-#define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
- INTEL_DEVID(dev_priv) == 0x1913 || \
- INTEL_DEVID(dev_priv) == 0x1916 || \
- INTEL_DEVID(dev_priv) == 0x1921 || \
- INTEL_DEVID(dev_priv) == 0x1926)
-#define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
- INTEL_DEVID(dev_priv) == 0x1915 || \
- INTEL_DEVID(dev_priv) == 0x191E)
-#define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
- INTEL_DEVID(dev_priv) == 0x5913 || \
- INTEL_DEVID(dev_priv) == 0x5916 || \
- INTEL_DEVID(dev_priv) == 0x5921 || \
- INTEL_DEVID(dev_priv) == 0x5926)
-#define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
- INTEL_DEVID(dev_priv) == 0x5915 || \
- INTEL_DEVID(dev_priv) == 0x591E)
-#define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
- INTEL_DEVID(dev_priv) == 0x87C0)
+#define IS_HSW_ULX(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
+#define IS_SKL_ULT(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
+#define IS_SKL_ULX(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
+#define IS_KBL_ULT(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
+#define IS_KBL_ULX(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
+#define IS_AML_ULX(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML_ULX)
#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 2)
#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
@@ -2365,16 +2415,16 @@ static inline unsigned int i915_sg_segment_size(void)
INTEL_INFO(dev_priv)->gt == 2)
#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 3)
-#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
- (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_ULT(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 2)
#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
INTEL_INFO(dev_priv)->gt == 3)
-#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
- (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
-#define IS_ICL_WITH_PORT_F(dev_priv) (IS_ICELAKE(dev_priv) && \
- INTEL_DEVID(dev_priv) != 0x8A51)
+#define IS_CNL_WITH_PORT_F(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
+#define IS_ICL_WITH_PORT_F(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 26bac517e383..16a9cfc806df 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -677,6 +677,9 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
err_printf(m, "Reset count: %u\n", error->reset_count);
err_printf(m, "Suspend count: %u\n", error->suspend_count);
err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
+ err_printf(m, "Subplatform: 0x%x\n",
+ intel_subplatform(&error->runtime_info,
+ error->device_info.platform));
err_print_pciid(m, m->i915);
err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4fa072a3280f..216ab56abe38 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -32,7 +32,7 @@
#include "i915_globals.h"
#include "i915_selftest.h"
-#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
+#define PLATFORM(x) .platform = (x)
#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
#define I845_PIPE_OFFSETS \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index eddf83807957..90127eb988f6 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -707,6 +707,72 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
return 0;
}
+void intel_device_info_subplatform_init(struct drm_i915_private *i915)
+{
+ const struct intel_device_info *info = INTEL_INFO(i915);
+ const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
+ const unsigned int pi = __platform_mask_index(rinfo, info->platform);
+ const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
+ u16 devid = INTEL_DEVID(i915);
+ u32 mask = 0;
+
+ RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
+
+ if (IS_HASWELL(i915)) {
+ if ((devid & 0xFF00) == 0x0A00)
+ mask |= BIT(INTEL_SUBPLATFORM_ULT);
+ /* ULX machines are also considered ULT. */
+ if (devid == 0x0A0E || devid == 0x0A1E)
+ mask |= BIT(INTEL_SUBPLATFORM_ULX);
+ } else if (IS_BROADWELL(i915)) {
+ if ((devid & 0xf) == 0x6 ||
+ (devid & 0xf) == 0xb ||
+ (devid & 0xf) == 0xe)
+ mask |= BIT(INTEL_SUBPLATFORM_ULT);
+ /* ULX machines are also considered ULT. */
+ if ((devid & 0xf) == 0xe)
+ mask |= BIT(INTEL_SUBPLATFORM_ULX);
+ } else if (IS_SKYLAKE(i915)) {
+ if (devid == 0x1906 ||
+ devid == 0x1913 ||
+ devid == 0x1916 ||
+ devid == 0x1921 ||
+ devid == 0x1926)
+ mask |= BIT(INTEL_SUBPLATFORM_ULT);
+ else if (devid == 0x190E ||
+ devid == 0x1915 ||
+ devid == 0x191E)
+ mask |= BIT(INTEL_SUBPLATFORM_ULX);
+ } else if (IS_KABYLAKE(i915)) {
+ if (devid == 0x5906 ||
+ devid == 0x5913 ||
+ devid == 0x5916 ||
+ devid == 0x5921 ||
+ devid == 0x5926)
+ mask |= BIT(INTEL_SUBPLATFORM_ULT);
+ else if (devid == 0x590E ||
+ devid == 0x5915 ||
+ devid == 0x591E)
+ mask |= BIT(INTEL_SUBPLATFORM_ULX);
+ else if (devid == 0x591C ||
+ devid == 0x87C0)
+ mask |= BIT(INTEL_SUBPLATFORM_AML_ULX);
+ } else if (IS_COFFEELAKE(i915)) {
+ if ((devid & 0x00F0) == 0x00A0)
+ mask |= BIT(INTEL_SUBPLATFORM_ULT);
+ } else if (IS_CANNONLAKE(i915)) {
+ if ((devid & 0x0004) == 0x0004)
+ mask |= BIT(INTEL_SUBPLATFORM_PORTF);
+ } else if (IS_ICELAKE(i915)) {
+ if (devid != 0x8A51)
+ mask |= BIT(INTEL_SUBPLATFORM_PORTF);
+ }
+
+ GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS);
+
+ RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
+}
+
/**
* intel_device_info_runtime_init - initialize runtime info
* @dev_priv: the i915 device
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6234570a9b17..5efcc10a8f99 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -76,6 +76,19 @@ enum intel_platform {
INTEL_MAX_PLATFORMS
};
+/*
+ * Subplatform bits share the same namespace per parent platform. In other words
+ * it is fine for the same bit to be used on multiple parent platforms.
+ */
+
+#define INTEL_SUBPLATFORM_BITS (3)
+
+#define INTEL_SUBPLATFORM_ULT (0)
+#define INTEL_SUBPLATFORM_ULX (1)
+#define INTEL_SUBPLATFORM_AML_ULX (2)
+
+#define INTEL_SUBPLATFORM_PORTF (0)
+
enum intel_ppgtt_type {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
@@ -159,7 +172,6 @@ struct intel_device_info {
intel_engine_mask_t engine_mask; /* Engines supported by the HW */
enum intel_platform platform;
- u32 platform_mask;
enum intel_ppgtt_type ppgtt_type;
unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
@@ -196,6 +208,16 @@ struct intel_device_info {
};
struct intel_runtime_info {
+ /*
+ * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
+ * into single runtime conditionals, and also to provide groundwork
+ * for future per platform, or per SKU build optimizations.
+ *
+ * Array can be extended when necessary if the corresponding
+ * BUILD_BUG_ON is hit.
+ */
+ u32 platform_mask[1];
+
u16 device_id;
u8 num_sprites[I915_MAX_PIPES];
@@ -270,6 +292,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
const char *intel_platform_name(enum intel_platform platform);
+void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump_flags(const struct intel_device_info *info,
struct drm_printer *p);
--
2.19.1
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