[Intel-gfx] [PATCH 6/6] drm/i915: Clean up gen2 DPLL readout

[Tvrtko Ursulin]

On 18/03/2019 16:56, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> The current gen2 DPLL readout code:
> * assumes i845/i865 have LVDS which is not true
> * assumes only pipe B can drive LVDS (true, but makes
>    the code appear a bit magical)
> * hard to parse in general
> 
> Clean it up by checking for i85x (the only gen2 platform
> with LVDS) and reusing intel_lvds_port_enabled().
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_display.c | 10 ++++++----
>   1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2ba61181746d..9f31d94fc04b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10809,7 +10809,6 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
>   {
>   	struct drm_device *dev = crtc->base.dev;
>   	struct drm_i915_private *dev_priv = to_i915(dev);
> -	int pipe = pipe_config->cpu_transcoder;
>   	u32 dpll = pipe_config->dpll_hw_state.dpll;
>   	u32 fp;
>   	struct dpll clock;
> @@ -10858,10 +10857,13 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
>   		else
>   			port_clock = i9xx_calc_dpll_params(refclk, &clock);
>   	} else {
> -		u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
> -		bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
> +		enum pipe lvds_pipe;
> +
> +		if (IS_I85X(dev_priv) &&
> +		    intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
> +		    lvds_pipe == crtc->pipe) {
> +			u32 lvds = I915_READ(LVDS);
>   
> -		if (is_lvds) {
>   			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
>   				       DPLL_FPA01_P1_POST_DIV_SHIFT);
>   
> 

I defer to domain experts on this one.

Regards,

Tvrtko