[Intel-gfx] [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated

[Shankar, Uma]

>-----Original Message-----
>From: Kulkarni, Vandita
>Sent: Wednesday, March 20, 2019 3:39 PM
>To: intel-gfx at lists.freedesktop.org
>Cc: Nikula, Jani <jani.nikula at intel.com>; Shankar, Uma <uma.shankar at intel.com>;
>Chauhan, Madhav <madhav.chauhan at intel.com>; Kulkarni, Vandita
><vandita.kulkarni at intel.com>
>Subject: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated

You can drop dsi from commit header. Just drm/i915/icl/ should be good.
Also update header as Ungate ddi clocks if gated

>
>IO enable sequencing needs ddi clocks enabled.
>These clocks will be gated at the later point in the enable sequence.
>
>Signed-off-by: Vandita Kulkarni <vandita.kulkarni at intel.com>
>---
> drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index
>beb30d9..f02504d 100644
>--- a/drivers/gpu/drm/i915/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/icl_dsi.c
>@@ -589,6 +589,14 @@ static void gen11_dsi_map_pll(struct intel_encoder
>*encoder,
> 		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> 	}
> 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>+
>+	/* make sure that the ddi clocks are not gated */
>+	val = I915_READ(DPCLKA_CFGCR0_ICL);
>+	for_each_dsi_port(port, intel_dsi->ports) {
>+		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
>+	}
>+	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>+
> 	POSTING_READ(DPCLKA_CFGCR0_ICL);

I think you can reuse the val from top and avoid an extra write to the same register.

Otherwise change looks ok to me. With above comments fixed,
Reviewed-by: Uma Shankar <uma.shankar at intel.com>

>
> 	mutex_unlock(&dev_priv->dpll_lock);
>--
>1.9.1