[Intel-gfx] [PATCH] drm/i915: set vdbox/vebox enable masks on all gens

[Daniele Ceraolo Spurio]

The upcoming unified GuC FW will require us to send video engine enable
masks to GuC for its initialization.

For consistency, just set the runtime_info enable masks for all gens.
We'll then be able to directly use those in the GuC setup

Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
Cc: John Spotswood <john.a.spotswood at intel.com>
Cc: Eric Betancourt <eric.s.betancourt at intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index eddf83807957..836184d6538e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -872,8 +872,14 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
 	unsigned int i;
 	u32 media_fuse;
 
-	if (INTEL_GEN(dev_priv) < 11)
+	if (INTEL_GEN(dev_priv) < 11) {
+		RUNTIME_INFO(dev_priv)->vdbox_enable =
+			(info->engine_mask & GENMASK(VCS0 + I915_MAX_VCS, VCS0)) >> VCS0;
+
+		RUNTIME_INFO(dev_priv)->vebox_enable =
+			(info->engine_mask & GENMASK(VECS0 + I915_MAX_VECS, VECS0)) >> VECS0;
 		return;
+	}
 
 	media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
 
-- 
2.20.1