[Intel-gfx] [PATCH] drm/i915: set vdbox/vebox enable masks on all gens

[Daniele Ceraolo Spurio]

On 3/21/19 3:11 PM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2019-03-21 22:02:06)
>> The upcoming unified GuC FW will require us to send video engine enable
>> masks to GuC for its initialization.
>>
>> For consistency, just set the runtime_info enable masks for all gens.
>> We'll then be able to directly use those in the GuC setup
>>
>> Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
>> Cc: John Spotswood <john.a.spotswood at intel.com>
>> Cc: Eric Betancourt <eric.s.betancourt at intel.com>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_device_info.c | 8 +++++++-
>>   1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index eddf83807957..836184d6538e 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -872,8 +872,14 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
>>          unsigned int i;
>>          u32 media_fuse;
>>   
>> -       if (INTEL_GEN(dev_priv) < 11)
>> +       if (INTEL_GEN(dev_priv) < 11) {
>> +               RUNTIME_INFO(dev_priv)->vdbox_enable =
>> +                       (info->engine_mask & GENMASK(VCS0 + I915_MAX_VCS, VCS0)) >> VCS0;

D'oh!

Thanks for catching this, GuC just ignores the higher bits and didn't 
complain, so I missed it.

Daniele

> 
> I915_MAX_V[E]CS is actually number of VCS, so this needs -1 on the high bit
> as it is inclusive.
> -Chris
>