[Intel-gfx] [v3 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi

[Shankar, Uma]

>-----Original Message-----
>From: Kulkarni, Vandita
>Sent: Monday, March 25, 2019 4:57 PM
>To: intel-gfx at lists.freedesktop.org
>Cc: Nikula, Jani <jani.nikula at intel.com>; Shankar, Uma <uma.shankar at intel.com>;
>Chauhan, Madhav <madhav.chauhan at intel.com>; Deak, Imre
><imre.deak at intel.com>; Syrjala, Ville <ville.syrjala at intel.com>; Kulkarni, Vandita
><vandita.kulkarni at intel.com>
>Subject: [v3 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi
>
>Re-enable clock gating of DDI clocks.
>
>v2: Fix the default ddi clk state for mipi-dsi (Imre)
>
>Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks)
>Signed-off-by: Vandita Kulkarni <vandita.kulkarni at intel.com>
>---
> drivers/gpu/drm/i915/icl_dsi.c   | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index
>4aef5dd..39d6410 100644
>--- a/drivers/gpu/drm/i915/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/icl_dsi.c
>@@ -1123,7 +1123,7 @@ static void gen11_dsi_disable_port(struct intel_encoder
>*encoder)
> 			DRM_ERROR("DDI port:%c buffer not idle\n",
> 				  port_name(port));
> 	}
>-	gen11_dsi_ungate_clocks(encoder);
>+	gen11_dsi_gate_clocks(encoder);
> }
>
> static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) diff --git
>a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>index 933df3a..976c010 100644
>--- a/drivers/gpu/drm/i915/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/intel_ddi.c
>@@ -2821,10 +2821,10 @@ void icl_sanitize_encoder_pll_mapping(struct
>intel_encoder *encoder)
> 				return;
> 		}
> 		/*
>-		 * DSI ports should have their DDI clock ungated when disabled
>-		 * and gated when enabled.
>+		 * For DSI we keep the ddi clocks gated
>+		 * except during enable/disable sequence.
> 		 */

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar at intel.com>

>-		ddi_clk_needed = !encoder->base.crtc;
>+		ddi_clk_needed = false;
> 	}
>
> 	val = I915_READ(DPCLKA_CFGCR0_ICL);
>--
>1.9.1