[Intel-gfx] [v6 10/16] drm/i915/icl: Add ICL Plane Degamma Register definition

[Shankar, Uma]

>-----Original Message-----
>From: Roper, Matthew D
>Sent: Monday, March 25, 2019 11:07 PM
>To: Shankar, Uma <uma.shankar at intel.com>
>Cc: intel-gfx at lists.freedesktop.org; Lankhorst, Maarten
><maarten.lankhorst at intel.com>; Syrjala, Ville <ville.syrjala at intel.com>; Sharma,
>Shashank <shashank.sharma at intel.com>
>Subject: Re: [v6 10/16] drm/i915/icl: Add ICL Plane Degamma Register definition
>
>On Tue, Mar 19, 2019 at 02:14:18PM +0530, Uma Shankar wrote:
>> Add register definitions for ICL Plane Degamma.
>>
>> Signed-off-by: Uma Shankar <uma.shankar at intel.com>
>
>Haven't reviewed the series in detail yet, just a couple drive-by comment below.
>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h | 42
>> +++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 42 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 0beed42..b9a2084 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -10181,6 +10181,48 @@ enum skl_power_gate {  #define
>> PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \
>>  				_PLANE_GAMC16_1(pipe),
>_PLANE_GAMC16_2(pipe))
>>
>> +/* Plane Color Register for Gen11+ */
>> +/* Plane Degamma Registers */
>> +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A	0x70100
>> +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B	0x71100
>> +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A	0x70200
>> +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B	0x71200
>
>Can you double check these ones?  I'm seeing them in the bspec at
>0x701D0 and such.

Yeah, looks like I clicked on the address definition to get more details and
webpage took me to a different page:
https://gfxspecs.intel.com/Predator/Home/Index/19766

I will fix this. Was wondering how I got these addresses wrong :)
Thanks Matt !!!

Regards,
Uma Shankar

>
>> +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe)	_PIPE(pipe,
>_PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A,
>_PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B)
>> +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)	_PIPE(pipe,
>_PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A,
>_PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B)
>> +
>> +#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i)
>	_MMIO_PLANE_GAMC(plane, i,
>_PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe),\
>> +
>_PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
>> +
>> +#define _PLANE_PRE_CSC_GAMC_INDEX_4_A		0x70400
>> +#define _PLANE_PRE_CSC_GAMC_INDEX_4_B		0x71400
>> +#define _PLANE_PRE_CSC_GAMC_INDEX_5_A		0x70500
>> +#define _PLANE_PRE_CSC_GAMC_INDEX_5_B		0x71500
>
>I think these ones are 0x704D0 and such as well.
>
>
>Matt
>
>> +#define _PLANE_PRE_CSC_GAMC_INDEX_4(pipe)	_PIPE(pipe,
>_PLANE_PRE_CSC_GAMC_INDEX_4_A, _PLANE_PRE_CSC_GAMC_INDEX_4_B)
>> +#define _PLANE_PRE_CSC_GAMC_INDEX_5(pipe)	_PIPE(pipe,
>_PLANE_PRE_CSC_GAMC_INDEX_5_A, _PLANE_PRE_CSC_GAMC_INDEX_5_B)
>> +
>> +#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i)
>	_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_4(pipe),\
>> +
>_PLANE_PRE_CSC_GAMC_INDEX_5(pipe))
>> +
>> +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A	0x701D4
>> +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B	0x711D4
>> +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A	0x702D4
>> +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B	0x712D4
>> +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe)	_PIPE(pipe,
>_PLANE_PRE_CSC_GAMC_DATA_ENH_1_A,
>_PLANE_PRE_CSC_GAMC_DATA_ENH_1_B)
>> +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe)	_PIPE(pipe,
>_PLANE_PRE_CSC_GAMC_DATA_ENH_2_A,
>_PLANE_PRE_CSC_GAMC_DATA_ENH_2_B)
>> +
>> +#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i)
>	_MMIO_PLANE_GAMC(plane, i,
>_PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe),\
>> +
>_PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
>> +
>> +#define _PLANE_PRE_CSC_GAMC_DATA_4_A		0x704D4
>> +#define _PLANE_PRE_CSC_GAMC_DATA_4_B		0x714D4
>> +#define _PLANE_PRE_CSC_GAMC_DATA_5_A		0x705D4
>> +#define _PLANE_PRE_CSC_GAMC_DATA_5_B		0x715D4
>> +#define _PLANE_PRE_CSC_GAMC_DATA_4(pipe)	_PIPE(pipe,
>_PLANE_PRE_CSC_GAMC_DATA_4_A, _PLANE_PRE_CSC_GAMC_DATA_4_B)
>> +#define _PLANE_PRE_CSC_GAMC_DATA_5(pipe)	_PIPE(pipe,
>_PLANE_PRE_CSC_GAMC_DATA_5_A, _PLANE_PRE_CSC_GAMC_DATA_5_B)
>> +
>> +#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i)
>	_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_4(pipe),\
>> +
>_PLANE_PRE_CSC_GAMC_DATA_5(pipe))
>> +
>>  /* pipe CSC & degamma/gamma LUTs on CHV */
>>  #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
>>  #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)
>> --
>> 1.9.1
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795