[Intel-gfx] [PATCH 28/30] drm/i915/guc: Correctly handle GuC interrupts on Gen11

[Chris Wilson]

Quoting Michal Wajdeczko (2019-03-29 22:11:16)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3dd971c09d52..c1b4fbd5f496 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -573,6 +573,44 @@ static void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
>         gen9_reset_guc_interrupts(dev_priv);
>  }
>  
> +static void gen11_reset_guc_interrupts(struct drm_i915_private *dev_priv)
> +{
> +       spin_lock_irq(&dev_priv->irq_lock);
> +
> +       while (gen11_reset_one_iir(dev_priv, 0, GEN11_GUC))
> +               ;

I have to say this and gen11_reset_rps_interupts() is brave. Are these
registers move than double-buffered? Should we throw in a '&& loops++ < 3'?
-Chris