[Intel-gfx] [PATCH v6 2/6] drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats

[Mun, Gwan-gyeong]

On Wed, 2019-05-08 at 20:32 +0300, Ville Syrjälä wrote:
> On Wed, May 08, 2019 at 11:17:53AM +0300, Gwan-gyeong Mun wrote:
> > SDP VSC Header and Data Block follow DP 1.4a spec, section
> > 2.2.5.7.5,
> > chapter "VSC SDP Payload for Pixel Encoding/Colorimetry Format".
> > 
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>
> > Reviewed-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
> > ---
> >  include/drm/drm_dp_helper.h | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> > 
> > diff --git a/include/drm/drm_dp_helper.h
> > b/include/drm/drm_dp_helper.h
> > index 97ce790a5b5a..3793bea7b7fe 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -1096,6 +1096,23 @@ struct edp_vsc_psr {
> >  	u8 DB8_31[24]; /* Reserved */
> >  } __packed;
> >  
> > +struct dp_vsc_sdp {
> > +	struct dp_sdp_header sdp_header;
> > +	u8 DB0; /* Stereo Interface */
> > +	u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
> > +	u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
> > +	u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
> > +	u8 DB4; /* CRC value bits 7:0 of the G or Y component */
> > +	u8 DB5; /* CRC value bits 15:8 of the G or Y component */
> > +	u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
> > +	u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
> > +	u8 DB8_15[8];  /* Reserved */
> > +	u8 DB16; /* Pixel Encoding and Colorimetry Formats */
> > +	u8 DB17; /* Dynamic Range and Component Bit Depth */
> > +	u8 DB18; /* Content Type */
> > +	u8 DB19_31[13]; /* Reserved */
> > +} __packed;
> 
> Isn't this the same thing we have for edp already? Just rename the
> edp
> struct and add the missing stuff?
> 
Okay, I'll rename struct edp_vsc_psr to general name of dp_sdp and will
add missing stuff.
> > +
> >  #define EDP_VSC_PSR_STATE_ACTIVE	(1<<0)
> >  #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
> >  #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
> > -- 
> > 2.21.0