[Intel-gfx] [PATCH] drm/i915: Fix the interpretation of MAX_PRE-EMPHASIS_REACHED bit inorder to pass Link Layer compliance test number 400.3.1.15

[Khaled Almahallawy]

According to DP 1.4 standard, if the source supports four pre-emphasis levels, then the source shall set the bit MAX_PRE-EMPHASIS_REACHED = 1 only when trasmitter programmed PRE-EMPHASIS_SET field (bits 4:3) to 11b (Level 3). Pre-emphasis level 3 is the maximum pre-emphasis level that the source supports.
Currently the MAX_PRE-EMPHASIS_REACHED bit is interpreted as the Max Pre-Emphasis level for certain Swing Level. This interpretation fails Link Layer compliance test 400.3.1.15 step 17 according to the following Fail condition: TRAINING_LANEx_SET.MAX_PRE-EMPHASIS_REACHED = 1 (check all active lanes) and the Source DUT supports pre-emphasis level 3 (9.5db).

Cc: Clint Taylor <Clinton.A.Taylor at intel.com>
Cc: Manasi Navare <manasi.d.navare at intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 20 --------------------
 drivers/gpu/drm/i915/intel_dp.c  |  2 +-
 2 files changed, 1 insertion(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0af47f343faa..6540c979c098 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2239,26 +2239,6 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 		DP_TRAIN_VOLTAGE_SWING_MASK;
 }
 
-/*
- * We assume that the full set of pre-emphasis values can be
- * used on all DDI platforms. Should that change we need to
- * rethink this code.
- */
-u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
-{
-	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
-		return DP_TRAIN_PRE_EMPH_LEVEL_3;
-	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
-		return DP_TRAIN_PRE_EMPH_LEVEL_2;
-	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
-		return DP_TRAIN_PRE_EMPH_LEVEL_1;
-	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
-	default:
-		return DP_TRAIN_PRE_EMPH_LEVEL_0;
-	}
-}
-
 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
 				   int level, enum intel_output_type type)
 {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 77ba4da6b981..f94759e45862 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3541,7 +3541,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
 	enum port port = encoder->port;
 
 	if (HAS_DDI(dev_priv)) {
-		return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
+		return DP_TRAIN_PRE_EMPH_LEVEL_3;
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
-- 
2.17.1