[Intel-gfx] [PATCH 1/5] drm/i915: Add two spaces before the SKL_DFSM registers

[Ramalingam C]

On 2019-10-25 at 17:13:19 -0700, José Roberto de Souza wrote:
> The next patches are going to touch this registers so here already
> fixing it for older registers and make it consistent with most of
> the other registers in this file.
> 
> Cc: Ramalingam C <ramalingam.c at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 746326784a4d..09cb43f4e976 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7663,15 +7663,15 @@ enum {
>  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
>  
>  #define SKL_DFSM			_MMIO(0x51000)
> -#define SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> -#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> -#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> -#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> -#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
> +#define   SKL_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
> +#define   SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
> +#define   SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> +#define   SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> +#define   SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> +#define   SKL_DFSM_PIPE_A_DISABLE	(1 << 30)
> +#define   SKL_DFSM_PIPE_B_DISABLE	(1 << 21)
> +#define   SKL_DFSM_PIPE_C_DISABLE	(1 << 28)
> +#define   TGL_DFSM_PIPE_D_DISABLE	(1 << 22)
Looks good to me.

Reviewed-by: Ramalingam C <ramalingam.c at intel.com>
>  
>  #define SKL_DSSM				_MMIO(0x51004)
>  #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
> -- 
> 2.23.0
>