[Intel-gfx] [PATCH 10/28] drm/i915/selftests: Perform some basic cycle counting of MI ops

[Chris Wilson]

Quoting Mika Kuoppala (2019-11-07 08:39:00)
> Chris Wilson <chris at chris-wilson.co.uk> writes:
> 
> > Some basic information that is useful to know, such as how many cycles
> > is a MI_NOOP.
> >
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > Cc: Anna Karas <anna.karas at intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> > ---
> >  .../i915/gem/selftests/i915_gem_object_blt.c  |  15 +-
> >  drivers/gpu/drm/i915/gt/selftest_engine_cs.c  | 339 +++++++++++++++++-
> >  drivers/gpu/drm/i915/i915_pci.c               |   6 +
> >  drivers/gpu/drm/i915/i915_selftest.h          |   4 +
> >  .../drm/i915/selftests/i915_perf_selftests.h  |  13 +
> >  .../gpu/drm/i915/selftests/i915_selftest.c    |  43 +++
> >  6 files changed, 417 insertions(+), 3 deletions(-)
> >  create mode 100644 drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
> >
> > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
> > index 146ba71ce797..17fc60aa123a 100644
> > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
> > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
> > @@ -527,8 +527,6 @@ static int igt_copy_blt_ctx0(void *arg)
> >  int i915_gem_object_blt_live_selftests(struct drm_i915_private *i915)
> >  {
> >       static const struct i915_subtest tests[] = {
> > -             SUBTEST(perf_fill_blt),
> > -             SUBTEST(perf_copy_blt),
> >               SUBTEST(igt_fill_blt),
> >               SUBTEST(igt_fill_blt_ctx0),
> >               SUBTEST(igt_copy_blt),
> > @@ -543,3 +541,16 @@ int i915_gem_object_blt_live_selftests(struct drm_i915_private *i915)
> >  
> >       return i915_live_subtests(tests, i915);
> >  }
> > +
> > +int i915_gem_object_blt_perf_selftests(struct drm_i915_private *i915)
> > +{
> > +     static const struct i915_subtest tests[] = {
> > +             SUBTEST(perf_fill_blt),
> > +             SUBTEST(perf_copy_blt),
> > +     };
> > +
> > +     if (intel_gt_is_wedged(&i915->gt))
> > +             return 0;
> > +
> > +     return i915_live_subtests(tests, i915);
> > +}
> > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> > index 3880f07c29b8..aa6b1997eddb 100644
> > --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> > @@ -4,7 +4,344 @@
> >   * Copyright © 2018 Intel Corporation
> >   */
> >  
> > -#include "../i915_selftest.h"
> > +#include <linux/sort.h>
> > +
> > +#include "intel_gt_pm.h"
> > +#include "intel_rps.h"
> > +
> > +#include "i915_selftest.h"
> > +#include "selftests/igt_flush_test.h"
> > +
> > +#define COUNT 5
> > +
> > +static int cmp_u32(const void *A, const void *B)
> > +{
> > +     const u32 *a = A, *b = B;
> > +
> > +     return *a - *b;
> > +}
> > +
> > +static void perf_begin(struct intel_gt *gt)
> > +{
> > +     intel_gt_pm_get(gt);
> > +
> > +     /* Boost gpufreq to max [waitboost] and keep it fixed */
> > +     atomic_inc(&gt->rps.num_waiters);
> > +     schedule_work(&gt->rps.work);
> > +     flush_work(&gt->rps.work);
> > +}
> > +
> > +static int perf_end(struct intel_gt *gt)
> > +{
> > +     atomic_dec(&gt->rps.num_waiters);
> > +     intel_gt_pm_put(gt);
> > +
> > +     return igt_flush_test(gt->i915);
> > +}
> > +
> > +static int write_timestamp(struct i915_request *rq, int slot)
> > +{
> > +     u32 cmd;
> > +     u32 *cs;
> > +
> > +     cs = intel_ring_begin(rq, 4);
> > +     if (IS_ERR(cs))
> > +             return PTR_ERR(cs);
> > +
> > +     cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> > +     if (INTEL_GEN(rq->i915) >= 8)
> > +             cmd++;
> > +     *cs++ = cmd;
> > +     *cs++ = rq->engine->mmio_base + 0x358;
> 
> we have RING_TIMESTAMP.

i915_reg_mmio_offset(RING_TIMESTAMP(rq->engine))
> 
> Test so short we don't need the UDW I suppose?

Yeah, if we need more than 32b cycles, people will start to notice :)
Back of envelope puts wrap at a ballpark of 5s. (Different machines have
different clocks, but assume 128ns baseline.) And we would need several
gigabytes of MI_NOOP. :)
-Chris