[Intel-gfx] [PATCH 26/27] drm/i915/gt: Refactor mocs loops into single control macro

[Chris Wilson]

Quoting Mika Kuoppala (2019-11-12 17:02:18)
> Chris Wilson <chris at chris-wilson.co.uk> writes:
> > +static u32 mocs_register(const struct intel_engine_cs *engine)
> > +{
> > +     static const u32 offset[] = {
> > +             [RCS0]  = 0x0c800,
> > +             [VCS0]  = 0x0c900,
> > +             [VCS1]  = 0x0ca00,
> > +             [VECS0] = 0x0cb00,
> > +             [BCS0]  = 0x0cc00,
> > +             [VCS2]  = 0x10000,

A bit of a quandary as

@@ -361,12 +361,12 @@ static void __init_mocs_table(struct intel_uncore *uncore,
 static u32 mocs_register(const struct intel_engine_cs *engine)
 {
        static const u32 offset[] = {
-               [RCS0]  = 0x0c800,
-               [VCS0]  = 0x0c900,
-               [VCS1]  = 0x0ca00,
-               [VECS0] = 0x0cb00,
-               [BCS0]  = 0x0cc00,
-               [VCS2]  = 0x10000,
+               [RCS0]  = i915_mmio_reg_offset(GEN9_GFX_MOCS(0)),
+               [VCS0]  = i915_mmio_reg_offset(GEN9_MFX0_MOCS(0)),
+               [VCS1]  = i915_mmio_reg_offset(GEN9_BLT_MOCS(0)),
+               [VECS0] = i915_mmio_reg_offset(GEN9_VEBOX_MOCS(0)),
+               [BCS0]  = i915_mmio_reg_offset(GEN9_MFX1_MOCS(0)),
+               [VCS2]  = i915_mmio_reg_offset(GEN11_MFX2_MOCS(0)),
        };

        GEM_BUG_ON(engine->id >= ARRAY_SIZE(offset));

does not compile as they do not evaluate to a constant.

The alternative is to have the raw offsets for the indexed macros to
build off.
-Chris