[Intel-gfx] [PATCH] drm/i915/tgl: Add DKL PHY vswing table for HDMI

[Souza, Jose]

On Mon, 2019-11-18 at 10:02 -0800, Matt Roper wrote:
> The bspec initially provided a single DKL PHY vswing table for both
> HDMI
> and DP, but was recently updated to include an independent table for
> HDMI.
> 

Thanks, I had that in my TODO list to finish TC legacy.

Reviewed-by: José Roberto de Souza <jose.souza at intel.com>

> Bspec: 49292
> Fixes: 978c3e539be2 ("drm/i915/tgl: Add dkl phy programming
> sequences")
> Cc: Clinton A Taylor <clinton.a.taylor at intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 29 ++++++++++++++++++++
> ----
>  1 file changed, 24 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 8f817de34460..a976606d21c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -593,7 +593,7 @@ struct tgl_dkl_phy_ddi_buf_trans {
>  	u32 dkl_de_emphasis_control;
>  };
>  
> -static const struct tgl_dkl_phy_ddi_buf_trans
> tgl_dkl_phy_ddi_translations[] = {
> +static const struct tgl_dkl_phy_ddi_buf_trans
> tgl_dkl_phy_dp_ddi_trans[] = {
>  				/* VS	pre-emp	Non-trans mV	Pre-
> emph dB */
>  	{ 0x7, 0x0, 0x00 },	/* 0	0	400mV		0 dB
> */
>  	{ 0x5, 0x0, 0x03 },	/* 0	1	400mV		3.5
> dB */
> @@ -607,6 +607,20 @@ static const struct tgl_dkl_phy_ddi_buf_trans
> tgl_dkl_phy_ddi_translations[] = {
>  	{ 0x0, 0x0, 0x00 },	/* 3	0	1200mV		0 dB
> HDMI default */
>  };
>  
> +static const struct tgl_dkl_phy_ddi_buf_trans
> tgl_dkl_phy_hdmi_ddi_trans[] = {
> +				/* HDMI Preset	VS	Pre-emph */
> +	{ 0x7, 0x0, 0x0 },	/* 1		400mV	0dB */
> +	{ 0x6, 0x0, 0x0 },	/* 2		500mV	0dB */
> +	{ 0x4, 0x0, 0x0 },	/* 3		650mV	0dB */
> +	{ 0x2, 0x0, 0x0 },	/* 4		800mV	0dB */
> +	{ 0x0, 0x0, 0x0 },	/* 5		1000mV	0dB */
> +	{ 0x0, 0x0, 0x5 },	/* 6		Full	-1.5 dB */
> +	{ 0x0, 0x0, 0x6 },	/* 7		Full	-1.8 dB */
> +	{ 0x0, 0x0, 0x7 },	/* 8		Full	-2 dB */
> +	{ 0x0, 0x0, 0x8 },	/* 9		Full	-2.5 dB */
> +	{ 0x0, 0x0, 0xA },	/* 10		Full	-3 dB */
> +};
> +
>  static const struct ddi_buf_trans *
>  bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int
> *n_entries)
>  {
> @@ -897,7 +911,7 @@ static int intel_ddi_hdmi_level(struct
> drm_i915_private *dev_priv, enum port por
>  			icl_get_combo_buf_trans(dev_priv,
> INTEL_OUTPUT_HDMI,
>  						0, &n_entries);
>  		else
> -			n_entries =
> ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
> +			n_entries =
> ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
>  		default_entry = n_entries - 1;
>  	} else if (INTEL_GEN(dev_priv) == 11) {
>  		if (intel_phy_is_combo(dev_priv, phy))
> @@ -2358,7 +2372,7 @@ u8 intel_ddi_dp_voltage_max(struct
> intel_encoder *encoder)
>  			icl_get_combo_buf_trans(dev_priv, encoder-
> >type,
>  						intel_dp->link_rate,
> &n_entries);
>  		else
> -			n_entries =
> ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
> +			n_entries =
> ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
>  	} else if (INTEL_GEN(dev_priv) == 11) {
>  		if (intel_phy_is_combo(dev_priv, phy))
>  			icl_get_combo_buf_trans(dev_priv, encoder-
> >type,
> @@ -2810,8 +2824,13 @@ tgl_dkl_phy_ddi_vswing_sequence(struct
> intel_encoder *encoder, int link_clock,
>  	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
>  	u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
>  
> -	n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
> -	ddi_translations = tgl_dkl_phy_ddi_translations;
> +	if (encoder->type == INTEL_OUTPUT_HDMI) {
> +		n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
> +		ddi_translations = tgl_dkl_phy_hdmi_ddi_trans;
> +	} else {
> +		n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
> +		ddi_translations = tgl_dkl_phy_dp_ddi_trans;
> +	}
>  
>  	if (level >= n_entries)
>  		level = n_entries - 1;