[Intel-gfx] [PATCH 07/17] drm/i915/gt: Only wait for register chipset flush if active

[Mika Kuoppala]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> Only serialise with the chipset using an mmio if the chipset is
> currently active. We expect that any writes into the chipset range will
> simply be forgotten until it wakes up.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

>From other threads,

Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index b5a9b87e4ec9..c4fd8d65b8a3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -304,7 +304,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
>  
>  	intel_gt_chipset_flush(gt);
>  
> -	with_intel_runtime_pm(uncore->rpm, wakeref) {
> +	with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
>  		unsigned long flags;
>  
>  		spin_lock_irqsave(&uncore->lock, flags);
> -- 
> 2.24.0