[Intel-gfx] Question on how i915/GEM is handling page faults

Christian König christian.koenig at amd.com
Wed Nov 20 12:18:32 UTC 2019

Previous message (by thread): [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable second dbuf slice for ICL and TGL (rev5)
Next message (by thread): [Intel-gfx] [CI] drm/i915: Mark up the calling context for intel_wakeref_put()
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

Hi Daniel,

how does i915/GEM lock dma_resv objects for CPU page faulting?

I've been wondering if a good bunch of ttm_bo_vm_reserve() wouldn't be 
better placed in the common dma_resv.c file.

Regards,
Christian.

Previous message (by thread): [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable second dbuf slice for ICL and TGL (rev5)
Next message (by thread): [Intel-gfx] [CI] drm/i915: Mark up the calling context for intel_wakeref_put()
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the Intel-gfx mailing list