[Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu

Navik, Ankit P ankit.p.navik at intel.com
Wed Nov 27 11:06:44 UTC 2019


Hi Chris, 

Thank you for your feedback.

> On 26/11/2019 10:52, Charis Wilson wrote:
> 
> Quoting Tvrtko Ursulin (2019-11-26 10:51:22)
> > You mentioned you did some experiment where you did something on
> > context pinning and that it did not work so well. I don't know what
> > that was though. I don't think that was ever posted?
> >
> > What I am thinking is this: You drop the timer altogether. Instead in
> > __execlists_update_reg_state you look at your gem_context->req_cnt and
> > implement your logic there.
> 
> I noticed the same non-sequitur. Except I would push that either the entire
> measurement and hence patch series is bogus (beyond the patches themselves
> being trivially broken, tested much?), or that it really should be done from a
> timer and also adjust pinned contexts ala reconfigure_sseu.
> 
> A bunch of selftests and igt proving that different sseu setups do consume
> different power (i.e. that we can adjust sseu correctly), along with
> demonstrating good workloads where autotuning produces beneficial results is
> a must.
> 
> Also given Tvrtko's stats, this could all be done from userspace with an extended
> CONTEXT_PARAM_SSEU, so why would we not do it that way?
> -Chris

We have verified this patch series on KBL, GLK & CML platforms with well
known standard benchmarks as mentioned in the cover letters.
Power savings are verified with various tools (RAPL counters, Moonsoon
power monitor and socwatch).
We have also verified Battery Life use cases which shows significant power
savings. So I hope you will understand the we have taken proper measurements
before pushing the patch series. 

Thanks & Regards, 
Ankit


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