[Intel-gfx] [PATCH v2 1/5] drm/i915/psr: Add bits per pixel limitation

[Matt Roper]

On Mon, Nov 25, 2019 at 04:53:56PM -0800, José Roberto de Souza wrote:
> PSR2 HW only support a limited number of bits per pixel, if mode has
> more than supported PSR2 should not be enabled.
> 
> BSpec: 50422
> BSpec: 7713
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index c1d133362b76..0d84ea28bc6f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -608,7 +608,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>  	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> -	int psr_max_h = 0, psr_max_v = 0;
> +	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
>  
>  	if (!dev_priv->psr.sink_psr2_support)
>  		return false;
> @@ -632,12 +632,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	if (INTEL_GEN(dev_priv) >= 12) {
>  		psr_max_h = 5120;
>  		psr_max_v = 3200;
> +		max_bpp = 30;
>  	} else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>  		psr_max_h = 4096;
>  		psr_max_v = 2304;
> +		max_bpp = 24;
>  	} else if (IS_GEN(dev_priv, 9)) {
>  		psr_max_h = 3640;
>  		psr_max_v = 2304;
> +		max_bpp = 24;
>  	}
>  
>  	if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
> @@ -647,6 +650,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  		return false;
>  	}
>  
> +	if (crtc_state->pipe_bpp > max_bpp) {
> +		DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max supported %d\n",
> +			      crtc_state->pipe_bpp, max_bpp);
> +		return false;
> +	}
> +
>  	/*
>  	 * HW sends SU blocks of size four scan lines, which means the starting
>  	 * X coordinate and Y granularity requirements will always be met. We
> -- 
> 2.24.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795