[Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Bump support for Tigerlake

[Chris Wilson]

There's very little variation in non-privileged registers for Tigerlake,
so we can mostly inherit the set from gen11. There is no whitelist at
present, so we do not need to add any special registers.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 tests/i915/gem_ctx_isolation.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index df1d655ae..819daafc3 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -55,10 +55,11 @@ enum {
 #define GEN9 (ALL << 9)
 #define GEN10 (ALL << 10)
 #define GEN11 (ALL << 11)
+#define GEN12 (ALL << 12)
 
 #define NOCTX 0
 
-#define LAST_KNOWN_GEN 11
+#define LAST_KNOWN_GEN 12
 
 static const struct named_register {
 	const char *name;
@@ -116,9 +117,9 @@ static const struct named_register {
 	{ "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
 	{ "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
 	{ "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
-	{ "L3_Config", GEN8, RCS0, 0x7034 },
-	{ "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0xffff },
-	{ "TD_CTL2", GEN8, RCS0, 0xe404 },
+	{ "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
+	{ "TD_CTL", GEN_RANGE(8, 11), RCS0, 0xe400, .write_mask = 0xffff },
+	{ "TD_CTL2", GEN_RANGE(8, 11), RCS0, 0xe404 },
 	{ "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
 	{ "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
 	{ "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
@@ -852,7 +853,7 @@ igt_main
 		gen = intel_gen(intel_get_drm_devid(fd));
 
 		igt_warn_on_f(gen > LAST_KNOWN_GEN,
-					  "GEN not recognized! Test needs to be updated to run.");
+			      "GEN not recognized! Test needs to be updated to run.");
 		igt_skip_on(gen > LAST_KNOWN_GEN);
 	}
 
-- 
2.23.0