[Intel-gfx] [PATCH 1/2] drm/i915: Fix audio power up sequence for gen10/11

[Imre Deak]

On Tue, Oct 01, 2019 at 07:35:54PM +0300, Kai Vehmanen wrote:
> On gen10/11 platforms, driver must set the enable bit of AUD_PIN_BUF_CTL
> as part of audio power up sequence.
> 
> Failing to do this resulted in errors during display audio codec probe,
> and failures during resume from suspend.

Good catch, seems to match bspec 21352 (and 49280 for GEN12+).

Before setting this bit the sequence has an other step done in the HDA
driver (LCTL reg write in sound/pci/hda/hda_intel.c, intel_init_lctl())
before setting this bit. If that order is important we'd need another
hook in drm_audio_component_ops (and also clear the bit).

> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111214
> Signed-off-by: Kai Vehmanen <kai.vehmanen at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_audio.c | 5 +++++
>  drivers/gpu/drm/i915/i915_reg.h            | 2 ++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 54638d99e021..a731af7ada08 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -862,6 +862,11 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
>  		/* Force CDCLK to 2*BCLK as long as we need audio powered. */
>  		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>  			glk_force_audio_cdclk(dev_priv, true);
> +
> +		if (INTEL_GEN(dev_priv) == 11 || INTEL_GEN(dev_priv) == 10)
> +			I915_WRITE(AUD_PIN_BUF_CTL,
> +				   (I915_READ(AUD_PIN_BUF_CTL) |
> +				    AUD_PIN_BUF_ENABLE));
>  	}
>  
>  	return ret;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 058aa5ca8b73..daff9058f0e8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9133,6 +9133,8 @@ enum {
>  #define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
>  
>  #define AUD_FREQ_CNTRL			_MMIO(0x65900)
> +#define AUD_PIN_BUF_CTL		_MMIO(0x48414)
> +#define   AUD_PIN_BUF_ENABLE		BIT(31)
>  
>  /*
>   * HSW - ICL power wells
> -- 
> 2.17.1
> 
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