[Intel-gfx] [PATCH] drm/i915/tgl: Add the Thunderbolt PLL divider values

[Imre Deak]

On Wed, Oct 02, 2019 at 11:07:21PM +0300, Souza, Jose wrote:
> On Wed, 2019-10-02 at 17:08 +0300, Imre Deak wrote:
> > The Thunderbolt PLL divider values on TGL differ from the ICL ones,
> > update the PLL parameter calculation function accordingly.
> > 
> > Bspec: 49204
> > 
> > Cc: Jose Souza <jose.souza at intel.com>
> > Cc: Clinton A Taylor <clinton.a.taylor at intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> > Cc: Mika Westerberg <mika.westerberg at intel.com>
> > Tested-by: Mika Westerberg <mika.westerberg at intel.com>
> > Signed-off-by: Imre Deak <imre.deak at intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 51
> > ++++++++++++++++++-
> >  1 file changed, 49 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index be69a2344294..7b0b18d95b07 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -2520,6 +2520,24 @@ static const struct skl_wrpll_params
> > icl_tbt_pll_19_2MHz_values = {
> >  	.pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio =
> > 0,
> >  };
> >  
> > +static const struct skl_wrpll_params tgl_tbt_pll_19_2MHz_values = {
> > +	.dco_integer = 0x54, .dco_fraction = 0x3000,
> > +	/* the following params are unused */
> > +	.pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
> > +};
> > +
> > +static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
> > +	.dco_integer = 0x43, .dco_fraction = 0x4000,
> > +	/* the following params are unused */
> > +	.pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
> > +};
> > +
> > +static const struct skl_wrpll_params tgl_tbt_pll_25MHz_values = {
> > +	.dco_integer = 0x40, .dco_fraction = 0x6666,
> > +	/* the following params are unused */
> > +	.pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
> > +};
> 
> 
> 25MHz reference frequency is not POR it was just a test by HW team and
> we don't even support it in icl_readout_refclk(), not sure if we should
> add it here.

Ah yes, thanks for spotting that, I missed that info in bspec. Will
remove it.

> 
> Other than that, LGTM:
> 
> Reviewed-by: José Roberto de Souza <jose.souza at intel.com>
> 
> > +
> >  static bool icl_calc_dp_combo_pll(struct intel_crtc_state
> > *crtc_state,
> >  				  struct skl_wrpll_params *pll_params)
> >  {
> > @@ -2547,8 +2565,37 @@ static bool icl_calc_tbt_pll(struct
> > intel_crtc_state *crtc_state,
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > >base.crtc->dev);
> >  
> > -	*pll_params = dev_priv->cdclk.hw.ref == 24000 ?
> > -			icl_tbt_pll_24MHz_values :
> > icl_tbt_pll_19_2MHz_values;
> > +	if (INTEL_GEN(dev_priv) >= 12) {
> > +		switch (dev_priv->cdclk.hw.ref) {
> > +		default:
> > +			MISSING_CASE(dev_priv->cdclk.hw.ref);
> > +			/* fall-through */
> > +		case 19200:
> > +		case 38400:
> > +			*pll_params = tgl_tbt_pll_19_2MHz_values;
> > +			break;
> > +		case 24000:
> > +			*pll_params = tgl_tbt_pll_24MHz_values;
> > +			break;
> > +		case 25000:
> > +			*pll_params = tgl_tbt_pll_25MHz_values;
> > +			break;
> > +		}
> > +	} else {
> > +		switch (dev_priv->cdclk.hw.ref) {
> > +		default:
> > +			MISSING_CASE(dev_priv->cdclk.hw.ref);
> > +			/* fall-through */
> > +		case 19200:
> > +		case 38400:
> > +			*pll_params = icl_tbt_pll_19_2MHz_values;
> > +			break;
> > +		case 24000:
> > +			*pll_params = icl_tbt_pll_24MHz_values;
> > +			break;
> > +		}
> > +	}
> > +
> >  	return true;
> >  }
> >