[Intel-gfx] [PATCH 08/24] drm/i915: Prepare to split crtc state in uapi and hw state
Ville Syrjälä
ville.syrjala at linux.intel.com
Tue Oct 8 17:06:43 UTC 2019
On Fri, Oct 04, 2019 at 01:34:58PM +0200, Maarten Lankhorst wrote:
> We want to split drm_crtc_state into the user visible state
> and actual hardware state. To prepare for this, we need some
> ground rules what should be in each state:
>
> In uapi we use:
> - crtc, *_changed flags, event, commit, state, mode_blob,
> (plane/connector/encoder)_mask.
>
> In hw state we use what's displayed in hardware:
> - enable, active, (adjusted) mode, color property blobs.
>
> clear_intel_crtc_state and hw readout need to be updated for these rules,
> which will allow us to enable 2 joined pipes.
I still have hard time with reading this patch. I still think it
would be easier to read if we didn't do both the "uapi" and "hw" changes
at the same time.
step 1.
struct drm_crtc_state uapi;
struct {
// hw state
} base;
step 2.
s/base/hw/
I think that would make it more obvious which parts of the code are
looking at which state.
>
> Note:
> - When making calling atomic_commit() you need to manipulate the uapi
> variables, atomic_check() will copy it to hw. This is because you're
> just another atomic client. Of course you can still check hw members
> at that point to decide if a pipe is active.
> - In general you should look at the hw members when available, unless
> there's a good reason to do something else.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 18 +-
> drivers/gpu/drm/i915/display/intel_atomic.c | 14 +-
> .../gpu/drm/i915/display/intel_atomic_plane.c | 6 +-
> drivers/gpu/drm/i915/display/intel_audio.c | 12 +-
> drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +-
> drivers/gpu/drm/i915/display/intel_color.c | 180 +++---
> drivers/gpu/drm/i915/display/intel_crt.c | 24 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 34 +-
> drivers/gpu/drm/i915/display/intel_display.c | 544 +++++++++---------
> drivers/gpu/drm/i915/display/intel_display.h | 6 +-
> .../drm/i915/display/intel_display_types.h | 28 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 42 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +-
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 14 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 +-
> drivers/gpu/drm/i915/display/intel_dvo.c | 14 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 64 +--
> drivers/gpu/drm/i915/display/intel_lspcon.c | 4 +-
> drivers/gpu/drm/i915/display/intel_lvds.c | 12 +-
> drivers/gpu/drm/i915/display/intel_panel.c | 14 +-
> drivers/gpu/drm/i915/display/intel_pipe_crc.c | 6 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c | 22 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 25 +-
> drivers/gpu/drm/i915/display/intel_tv.c | 8 +-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +-
> drivers/gpu/drm/i915/display/vlv_dsi.c | 20 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 14 +-
> drivers/gpu/drm/i915/intel_pm.c | 170 +++---
> 31 files changed, 700 insertions(+), 665 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 6e398c33a524..0e24b8e257e5 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -276,7 +276,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
>
> if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> const struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
> u32 dss_ctl2;
> u16 hactive = adjusted_mode->crtc_hdisplay;
> u16 dl_buffer_depth;
> @@ -625,7 +625,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> enum pipe pipe = intel_crtc->pipe;
> u32 tmp;
> enum port port;
> @@ -768,7 +768,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> const struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
> enum port port;
> enum transcoder dsi_trans;
> /* horizontal timings */
> @@ -1216,7 +1216,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
> {
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
>
> if (intel_dsi->dual_link) {
> adjusted_mode->crtc_hdisplay *= 2;
> @@ -1242,16 +1242,16 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>
> /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> pipe_config->port_clock =
> cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
>
> - pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
> + pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
> if (intel_dsi->dual_link)
> - pipe_config->base.adjusted_mode.crtc_clock *= 2;
> + pipe_config->hw.adjusted_mode.crtc_clock *= 2;
>
> gen11_dsi_get_timings(encoder, pipe_config);
> pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
> @@ -1265,11 +1265,11 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
> struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
> base);
> struct intel_connector *intel_connector = intel_dsi->attached_connector;
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> const struct drm_display_mode *fixed_mode =
> intel_connector->panel.fixed_mode;
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
>
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> intel_fixed_panel_mode(fixed_mode, adjusted_mode);
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index e6cb85d41c8d..7cf13b9c7d38 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -186,13 +186,14 @@ intel_digital_connector_duplicate_state(struct drm_connector *connector)
> struct drm_crtc_state *
> intel_crtc_duplicate_state(struct drm_crtc *crtc)
> {
> + const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state);
> struct intel_crtc_state *crtc_state;
>
> - crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL);
> + crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
> if (!crtc_state)
> return NULL;
>
> - __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base);
> + __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
>
> crtc_state->update_pipe = false;
> crtc_state->disable_lp_wm = false;
> @@ -204,7 +205,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> crtc_state->fb_bits = 0;
> crtc_state->update_planes = 0;
>
> - return &crtc_state->base;
> + return &crtc_state->uapi;
> }
>
> /**
> @@ -219,7 +220,10 @@ void
> intel_crtc_destroy_state(struct drm_crtc *crtc,
> struct drm_crtc_state *state)
> {
> - drm_atomic_helper_crtc_destroy_state(crtc, state);
> + struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
> +
> + __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
> + kfree(crtc_state);
> }
>
> static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
> @@ -315,7 +319,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> {
> struct intel_crtc_scaler_state *scaler_state =
> &crtc_state->scaler_state;
> - struct drm_atomic_state *drm_state = crtc_state->base.state;
> + struct drm_atomic_state *drm_state = crtc_state->uapi.state;
> struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
> int num_scalers_need;
> int i;
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 4eaab0de98bf..ca82167d4ce3 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -271,7 +271,7 @@ void intel_update_plane(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> trace_intel_update_plane(&plane->base, crtc);
> plane->update_plane(plane, crtc_state, plane_state);
> @@ -281,7 +281,7 @@ void intel_update_slave(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> trace_intel_update_plane(&plane->base, crtc);
> plane->update_slave(plane, crtc_state, plane_state);
> @@ -290,7 +290,7 @@ void intel_update_slave(struct intel_plane *plane,
> void intel_disable_plane(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> trace_intel_disable_plane(&plane->base, crtc);
> plane->disable_plane(plane, crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 54638d99e021..19b2af4b9f81 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -233,7 +233,7 @@ static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
> static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
> {
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> int i;
>
> for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
> @@ -554,7 +554,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder,
> const struct drm_connector_state *old_conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
> enum port port = encoder->port;
> u32 tmp, eldv;
> @@ -601,7 +601,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_connector *connector = conn_state->connector;
> enum pipe pipe = crtc->pipe;
> enum port port = encoder->port;
> @@ -691,10 +691,10 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct i915_audio_component *acomp = dev_priv->audio_component;
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_connector *connector = conn_state->connector;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> enum port port = encoder->port;
> enum pipe pipe = crtc->pipe;
>
> @@ -752,7 +752,7 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct i915_audio_component *acomp = dev_priv->audio_component;
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> enum port port = encoder->port;
> enum pipe pipe = crtc->pipe;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 22e83f857de8..3f6e29f61323 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -297,7 +297,7 @@ static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_stat
>
> static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> unsigned int data_rate = 0;
> enum plane_id plane_id;
>
> @@ -318,7 +318,7 @@ static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_
> void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> bw_state->data_rate[crtc->pipe] =
> intel_bw_crtc_data_rate(crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 42bd02638d32..e7e952f0eac0 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1917,10 +1917,10 @@ static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
> int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv =
> - to_i915(crtc_state->base.crtc->dev);
> + to_i915(crtc_state->uapi.crtc->dev);
> int min_cdclk;
>
> - if (!crtc_state->base.enable)
> + if (!crtc_state->hw.enable)
> return 0;
>
> min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
> @@ -2043,7 +2043,7 @@ static u8 bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> sizeof(state->min_voltage_level));
>
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> - if (crtc_state->base.enable)
> + if (crtc_state->hw.enable)
> state->min_voltage_level[i] =
> crtc_state->min_voltage_level;
> else
> @@ -2129,7 +2129,7 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
> vco = dev_priv->skl_preferred_vco_freq;
>
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> - if (!crtc_state->base.enable)
> + if (!crtc_state->hw.enable)
> continue;
>
> if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> @@ -2256,11 +2256,11 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
> if (IS_ERR(crtc_state))
> return PTR_ERR(crtc_state);
>
> - if (!crtc_state->base.active ||
> - drm_atomic_crtc_needs_modeset(&crtc_state->base))
> + if (!crtc_state->hw.active ||
> + drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> continue;
>
> - crtc_state->base.mode_changed = true;
> + crtc_state->uapi.mode_changed = true;
>
> ret = drm_atomic_add_affected_connectors(&state->base,
> &crtc->base);
> @@ -2313,7 +2313,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
> crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> if (crtc_state &&
> - drm_atomic_crtc_needs_modeset(&crtc_state->base))
> + drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> pipe = INVALID_PIPE;
> } else {
> pipe = INVALID_PIPE;
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 1e3a623eaf82..703e5e70b4e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -117,10 +117,10 @@ static bool lut_is_legacy(const struct drm_property_blob *lut)
>
> static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)
> {
> - return !crtc_state->base.degamma_lut &&
> - !crtc_state->base.ctm &&
> - crtc_state->base.gamma_lut &&
> - lut_is_legacy(crtc_state->base.gamma_lut);
> + return !crtc_state->hw.degamma_lut &&
> + !crtc_state->hw.ctm &&
> + crtc_state->hw.gamma_lut &&
> + lut_is_legacy(crtc_state->hw.gamma_lut);
> }
>
> /*
> @@ -205,7 +205,7 @@ static void icl_update_output_csc(struct intel_crtc *crtc,
>
> static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> /*
> * FIXME if there's a gamma LUT after the CSC, we should
> @@ -219,7 +219,7 @@ static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
> static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> u16 coeffs[9])
> {
> - const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
> + const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> const u64 *input;
> u64 temp[9];
> int i;
> @@ -270,11 +270,11 @@ static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
>
> static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> bool limited_color_range = ilk_csc_limited_range(crtc_state);
>
> - if (crtc_state->base.ctm) {
> + if (crtc_state->hw.ctm) {
> u16 coeff[9];
>
> ilk_csc_convert_ctm(crtc_state, coeff);
> @@ -309,10 +309,10 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>
> static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - if (crtc_state->base.ctm) {
> + if (crtc_state->hw.ctm) {
> u16 coeff[9];
>
> ilk_csc_convert_ctm(crtc_state, coeff);
> @@ -338,12 +338,12 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> */
> static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> - if (crtc_state->base.ctm) {
> - const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
> + if (crtc_state->hw.ctm) {
> + const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> u16 coeffs[9] = {};
> int i;
>
> @@ -404,7 +404,7 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
> static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
> const struct drm_property_blob *blob)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> int i;
> @@ -435,12 +435,12 @@ static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
>
> static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
> + i9xx_load_luts_internal(crtc_state, crtc_state->hw.gamma_lut);
> }
>
> static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> u32 val;
> @@ -453,7 +453,7 @@ static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
>
> static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> u32 val;
> @@ -468,7 +468,7 @@ static void ilk_color_commit(const struct intel_crtc_state *crtc_state)
>
> static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
> @@ -478,7 +478,7 @@ static void hsw_color_commit(const struct intel_crtc_state *crtc_state)
>
> static void skl_color_commit(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> u32 val = 0;
> @@ -524,8 +524,8 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
>
> static void i965_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> i9xx_load_luts(crtc_state);
> @@ -547,8 +547,8 @@ static void ilk_load_lut_10(struct intel_crtc *crtc,
>
> static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
>
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> i9xx_load_luts(crtc_state);
> @@ -654,9 +654,9 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
>
> static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> - const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> + const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
> i9xx_load_luts(crtc_state);
> @@ -677,9 +677,9 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
>
> static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> - const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> + const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
> i9xx_load_luts(crtc_state);
> @@ -700,11 +700,11 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
>
> static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> - const struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
> + const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
> u32 i;
>
> /*
> @@ -739,7 +739,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
>
> static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> @@ -766,8 +766,8 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
>
> static void glk_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> /*
> * On GLK+ both pipe CSC and degamma LUT are controlled
> @@ -777,7 +777,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
> * the degama LUT so that we don't have to reload
> * it every time the pipe CSC is being enabled.
> */
> - if (crtc_state->base.degamma_lut)
> + if (crtc_state->hw.degamma_lut)
> glk_load_degamma_lut(crtc_state);
> else
> glk_load_degamma_lut_linear(crtc_state);
> @@ -808,7 +808,7 @@ static void
> icl_load_gcmax(const struct intel_crtc_state *crtc_state,
> const struct drm_color_lut *color)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_dsb *dsb = intel_dsb_get(crtc);
> enum pipe pipe = crtc->pipe;
>
> @@ -822,8 +822,8 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
> static void
> icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
> const struct drm_color_lut *lut = blob->data;
> struct intel_dsb *dsb = intel_dsb_get(crtc);
> enum pipe pipe = crtc->pipe;
> @@ -854,8 +854,8 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
> static void
> icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
> const struct drm_color_lut *lut = blob->data;
> const struct drm_color_lut *entry;
> struct intel_dsb *dsb = intel_dsb_get(crtc);
> @@ -910,11 +910,11 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
>
> static void icl_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_dsb *dsb = intel_dsb_get(crtc);
>
> - if (crtc_state->base.degamma_lut)
> + if (crtc_state->hw.degamma_lut)
> glk_load_degamma_lut(crtc_state);
>
> switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
> @@ -990,9 +990,9 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
>
> static void chv_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> - const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> + const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
>
> cherryview_load_csc_matrix(crtc_state);
>
> @@ -1010,28 +1010,28 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
>
> void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> dev_priv->display.load_luts(crtc_state);
> }
>
> void intel_color_commit(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> dev_priv->display.color_commit(crtc_state);
> }
>
> int intel_color_check(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> return dev_priv->display.color_check(crtc_state);
> }
>
> void intel_color_get_config(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> if (dev_priv->display.read_luts)
> dev_priv->display.read_luts(crtc_state);
> @@ -1055,16 +1055,16 @@ static bool need_plane_update(struct intel_plane *plane,
> static int
> intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_atomic_state *state =
> - to_intel_atomic_state(new_crtc_state->base.state);
> + to_intel_atomic_state(new_crtc_state->uapi.state);
> const struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(state, crtc);
> struct intel_plane *plane;
>
> - if (!new_crtc_state->base.active ||
> - drm_atomic_crtc_needs_modeset(&new_crtc_state->base))
> + if (!new_crtc_state->hw.active ||
> + drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
> return 0;
>
> if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
> @@ -1107,9 +1107,9 @@ static int check_lut_size(const struct drm_property_blob *lut, int expected)
>
> static int check_luts(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> - const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> + const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
> int gamma_length, degamma_length;
> u32 gamma_tests, degamma_tests;
>
> @@ -1157,7 +1157,7 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state)
> return ret;
>
> crtc_state->gamma_enable =
> - crtc_state->base.gamma_lut &&
> + crtc_state->hw.gamma_lut &&
> !crtc_state->c8_planes;
>
> crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
> @@ -1176,11 +1176,11 @@ static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
> if (crtc_state_is_legacy_gamma(crtc_state))
> return 0;
>
> - if (crtc_state->base.degamma_lut)
> + if (crtc_state->hw.degamma_lut)
> cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
> - if (crtc_state->base.ctm)
> + if (crtc_state->hw.ctm)
> cgm_mode |= CGM_PIPE_MODE_CSC;
> - if (crtc_state->base.gamma_lut)
> + if (crtc_state->hw.gamma_lut)
> cgm_mode |= CGM_PIPE_MODE_GAMMA;
>
> return cgm_mode;
> @@ -1254,7 +1254,7 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state)
> return ret;
>
> crtc_state->gamma_enable =
> - crtc_state->base.gamma_lut &&
> + crtc_state->hw.gamma_lut &&
> !crtc_state->c8_planes;
>
> /*
> @@ -1280,8 +1280,8 @@ static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
> if (!crtc_state->gamma_enable ||
> crtc_state_is_legacy_gamma(crtc_state))
> return GAMMA_MODE_MODE_8BIT;
> - else if (crtc_state->base.gamma_lut &&
> - crtc_state->base.degamma_lut)
> + else if (crtc_state->hw.gamma_lut &&
> + crtc_state->hw.degamma_lut)
> return GAMMA_MODE_MODE_SPLIT;
> else
> return GAMMA_MODE_MODE_10BIT;
> @@ -1295,7 +1295,7 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
> * CSC comes after the LUT in degamma, RGB->YCbCr,
> * and RGB full->limited range mode.
> */
> - if (crtc_state->base.degamma_lut ||
> + if (crtc_state->hw.degamma_lut ||
> crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> limited_color_range)
> return 0;
> @@ -1313,13 +1313,13 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
> return ret;
>
> crtc_state->gamma_enable =
> - (crtc_state->base.gamma_lut ||
> - crtc_state->base.degamma_lut) &&
> + (crtc_state->hw.gamma_lut ||
> + crtc_state->hw.degamma_lut) &&
> !crtc_state->c8_planes;
>
> crtc_state->csc_enable =
> crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> - crtc_state->base.ctm || limited_color_range;
> + crtc_state->hw.ctm || limited_color_range;
>
> crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
>
> @@ -1350,14 +1350,14 @@ static int glk_color_check(struct intel_crtc_state *crtc_state)
> return ret;
>
> crtc_state->gamma_enable =
> - crtc_state->base.gamma_lut &&
> + crtc_state->hw.gamma_lut &&
> !crtc_state->c8_planes;
>
> /* On GLK+ degamma LUT is controlled by csc_enable */
> crtc_state->csc_enable =
> - crtc_state->base.degamma_lut ||
> + crtc_state->hw.degamma_lut ||
> crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> - crtc_state->base.ctm || crtc_state->limited_color_range;
> + crtc_state->hw.ctm || crtc_state->limited_color_range;
>
> crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
>
> @@ -1374,14 +1374,14 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
> {
> u32 gamma_mode = 0;
>
> - if (crtc_state->base.degamma_lut)
> + if (crtc_state->hw.degamma_lut)
> gamma_mode |= PRE_CSC_GAMMA_ENABLE;
>
> - if (crtc_state->base.gamma_lut &&
> + if (crtc_state->hw.gamma_lut &&
> !crtc_state->c8_planes)
> gamma_mode |= POST_CSC_GAMMA_ENABLE;
>
> - if (!crtc_state->base.gamma_lut ||
> + if (!crtc_state->hw.gamma_lut ||
> crtc_state_is_legacy_gamma(crtc_state))
> gamma_mode |= GAMMA_MODE_MODE_8BIT;
> else
> @@ -1394,7 +1394,7 @@ static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
> {
> u32 csc_mode = 0;
>
> - if (crtc_state->base.ctm)
> + if (crtc_state->hw.ctm)
> csc_mode |= ICL_CSC_ENABLE;
>
> if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
> @@ -1471,7 +1471,7 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
>
> int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (!crtc_state->gamma_enable)
> @@ -1580,7 +1580,7 @@ static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
> static struct drm_property_blob *
> i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> struct drm_property_blob *blob;
> @@ -1614,13 +1614,13 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
>
> static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
> {
> - crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> }
>
> static struct drm_property_blob *
> i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> enum pipe pipe = crtc->pipe;
> @@ -1661,15 +1661,15 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
> static void i965_read_luts(struct intel_crtc_state *crtc_state)
> {
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> - crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> - crtc_state->base.gamma_lut = i965_read_lut_10p6(crtc_state);
> + crtc_state->uapi.gamma_lut = i965_read_lut_10p6(crtc_state);
> }
>
> static struct drm_property_blob *
> chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> enum pipe pipe = crtc->pipe;
> @@ -1703,15 +1703,15 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
> static void chv_read_luts(struct intel_crtc_state *crtc_state)
> {
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> - crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> - crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);
> + crtc_state->uapi.gamma_lut = chv_read_cgm_lut(crtc_state);
> }
>
> static struct drm_property_blob *
> ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> enum pipe pipe = crtc->pipe;
> @@ -1744,15 +1744,15 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
> static void ilk_read_luts(struct intel_crtc_state *crtc_state)
> {
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> - crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> - crtc_state->base.gamma_lut = ilk_read_lut_10(crtc_state);
> + crtc_state->uapi.gamma_lut = ilk_read_lut_10(crtc_state);
> }
>
> static struct drm_property_blob *
> glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> int hw_lut_size = ivb_lut_10_size(prec_index);
> enum pipe pipe = crtc->pipe;
> @@ -1790,9 +1790,9 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
> static void glk_read_luts(struct intel_crtc_state *crtc_state)
> {
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> - crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> - crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> + crtc_state->uapi.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> }
>
> void intel_color_init(struct intel_crtc *crtc)
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index ff6126ea793c..164af1936d38 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -132,9 +132,9 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
> {
> pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
>
> - pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
> + pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
>
> - pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
> + pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
> }
>
> static void hsw_crt_get_config(struct intel_encoder *encoder,
> @@ -144,13 +144,13 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
>
> intel_ddi_get_config(encoder, pipe_config);
>
> - pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
> + pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
> DRM_MODE_FLAG_NHSYNC |
> DRM_MODE_FLAG_PVSYNC |
> DRM_MODE_FLAG_NVSYNC);
> - pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
> + pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
>
> - pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
> + pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
> }
>
> /* Note: The caller is required to filter out dpms modes not supported by the
> @@ -161,8 +161,8 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_crt *crt = intel_encoder_to_crt(encoder);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> u32 adpa;
>
> if (INTEL_GEN(dev_priv) >= 5)
> @@ -271,7 +271,7 @@ static void hsw_pre_enable_crt(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
>
> WARN_ON(!crtc_state->has_pch_encoder);
> @@ -288,7 +288,7 @@ static void hsw_enable_crt(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
>
> WARN_ON(!crtc_state->has_pch_encoder);
> @@ -358,7 +358,7 @@ static int intel_crt_compute_config(struct intel_encoder *encoder,
> struct drm_connector_state *conn_state)
> {
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
> @@ -373,7 +373,7 @@ static int pch_crt_compute_config(struct intel_encoder *encoder,
> struct drm_connector_state *conn_state)
> {
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
> @@ -390,7 +390,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3c1e885e0187..052caf2372d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1527,7 +1527,7 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
> if (pipe_config->pixel_multiplier)
> dotclock /= pipe_config->pixel_multiplier;
>
> - pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> + pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
> }
>
> static void icl_ddi_clock_get(struct intel_encoder *encoder,
> @@ -1742,7 +1742,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
>
> void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> u32 temp;
> @@ -1802,7 +1802,7 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
> void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
> bool state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> u32 temp;
> @@ -1824,7 +1824,7 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
> static u32
> intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> @@ -1856,9 +1856,9 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
> BUG();
> }
>
> - if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
> + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
> temp |= TRANS_DDI_PVSYNC;
> - if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
> + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
> temp |= TRANS_DDI_PHSYNC;
>
> if (cpu_transcoder == TRANSCODER_EDP) {
> @@ -1911,7 +1911,7 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
>
> void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> u32 temp;
> @@ -1927,7 +1927,7 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
> static void
> intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> u32 temp;
> @@ -1939,7 +1939,7 @@ intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
>
> void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
> @@ -2237,7 +2237,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
>
> void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
> enum port port = encoder->port;
> @@ -2255,7 +2255,7 @@ void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
>
> void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> if (cpu_transcoder != TRANSCODER_EDP) {
> @@ -3562,7 +3562,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -3987,7 +3987,7 @@ intel_ddi_update_prepare(struct intel_atomic_state *state,
> WARN_ON(crtc && crtc->active);
>
> intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
> - if (crtc_state && crtc_state->base.active)
> + if (crtc_state && crtc_state->hw.active)
> intel_update_active_dpll(state, crtc, encoder);
> }
>
> @@ -4117,7 +4117,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> u32 temp, flags = 0;
>
> @@ -4135,7 +4135,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> else
> flags |= DRM_MODE_FLAG_NVSYNC;
>
> - pipe_config->base.adjusted_mode.flags |= flags;
> + pipe_config->hw.adjusted_mode.flags |= flags;
>
> switch (temp & TRANS_DDI_BPC_MASK) {
> case TRANS_DDI_BPC_6:
> @@ -4281,7 +4281,7 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> int ret;
> @@ -4412,7 +4412,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder,
>
> WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
>
> - if (!crtc_state->base.active)
> + if (!crtc_state->hw.active)
> return 0;
>
> if (!crtc_state->hdmi_high_tmds_clock_ratio &&
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ecb15420b5ca..f555ff6b1f6a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -516,7 +516,7 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
> static bool
> needs_modeset(const struct intel_crtc_state *state)
> {
> - return drm_atomic_crtc_needs_modeset(&state->base);
> + return drm_atomic_crtc_needs_modeset(&state->uapi);
> }
>
> /*
> @@ -630,7 +630,7 @@ i9xx_select_p2_div(const struct intel_limit *limit,
> const struct intel_crtc_state *crtc_state,
> int target)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
> /*
> @@ -666,7 +666,7 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> {
> - struct drm_device *dev = crtc_state->base.crtc->dev;
> + struct drm_device *dev = crtc_state->uapi.crtc->dev;
> struct dpll clock;
> int err = target;
>
> @@ -724,7 +724,7 @@ pnv_find_best_dpll(const struct intel_limit *limit,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> {
> - struct drm_device *dev = crtc_state->base.crtc->dev;
> + struct drm_device *dev = crtc_state->uapi.crtc->dev;
> struct dpll clock;
> int err = target;
>
> @@ -780,7 +780,7 @@ g4x_find_best_dpll(const struct intel_limit *limit,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> {
> - struct drm_device *dev = crtc_state->base.crtc->dev;
> + struct drm_device *dev = crtc_state->uapi.crtc->dev;
> struct dpll clock;
> int max_n;
> bool found = false;
> @@ -874,7 +874,7 @@ vlv_find_best_dpll(const struct intel_limit *limit,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> struct dpll clock;
> unsigned int bestppm = 1000000;
> @@ -934,7 +934,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
> int target, int refclk, struct dpll *match_clock,
> struct dpll *best_clock)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> unsigned int best_error_ppm;
> struct dpll clock;
> @@ -1013,7 +1013,7 @@ bool intel_crtc_active(struct intel_crtc *crtc)
> * for atomic.
> */
> return crtc->active && crtc->base.primary->state->fb &&
> - crtc->config->base.adjusted_mode.crtc_clock;
> + crtc->config->hw.adjusted_mode.crtc_clock;
> }
>
> enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
> @@ -1067,7 +1067,7 @@ static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
> static void
> intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (INTEL_GEN(dev_priv) >= 4) {
> @@ -1526,7 +1526,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
>
> static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -1617,7 +1617,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
>
> static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> i915_reg_t reg;
> @@ -1761,7 +1761,7 @@ enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
>
> static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> /*
> * On i965gm the hardware frame counter reads
> @@ -1781,7 +1781,7 @@ static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state
>
> static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> drm_crtc_set_max_vblank_count(&crtc->base,
> intel_crtc_max_vblank_count(crtc_state));
> @@ -1790,7 +1790,7 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
>
> static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> enum pipe pipe = crtc->pipe;
> @@ -1848,7 +1848,7 @@ static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
>
> static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> enum pipe pipe = crtc->pipe;
> @@ -3114,14 +3114,14 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
> plane_state->base.visible = visible;
>
> if (visible)
> - crtc_state->base.plane_mask |= drm_plane_mask(&plane->base);
> + crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
> else
> - crtc_state->base.plane_mask &= ~drm_plane_mask(&plane->base);
> + crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
> }
>
> static void fixup_active_planes(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> struct drm_plane *plane;
>
> /*
> @@ -3132,7 +3132,7 @@ static void fixup_active_planes(struct intel_crtc_state *crtc_state)
> crtc_state->active_planes = 0;
>
> drm_for_each_plane_mask(plane, &dev_priv->drm,
> - crtc_state->base.plane_mask)
> + crtc_state->uapi.plane_mask)
> crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
> }
>
> @@ -3606,7 +3606,7 @@ i9xx_plane_max_stride(struct intel_plane *plane,
>
> static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 dspcntr = 0;
>
> @@ -3760,7 +3760,7 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
> return ret;
>
> ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> - &crtc_state->base,
> + &crtc_state->uapi,
> DRM_PLANE_HELPER_NO_SCALING,
> DRM_PLANE_HELPER_NO_SCALING,
> i9xx_plane_has_windowing(plane),
> @@ -3936,7 +3936,7 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
> */
> static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> const struct intel_crtc_scaler_state *scaler_state =
> &crtc_state->scaler_state;
> int i;
> @@ -4131,7 +4131,7 @@ static u32 cnl_plane_ctl_flip(unsigned int reflect)
>
> u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> u32 plane_ctl = 0;
>
> if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> @@ -4187,7 +4187,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>
> u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> u32 plane_color_ctl = 0;
>
> if (INTEL_GEN(dev_priv) >= 11)
> @@ -4803,7 +4803,7 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
>
> static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> enum pipe pipe = intel_crtc->pipe;
> i915_reg_t reg;
> @@ -4964,9 +4964,9 @@ void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
> /* Program iCLKIP clock to the desired frequency */
> static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - int clock = crtc_state->base.adjusted_mode.crtc_clock;
> + int clock = crtc_state->hw.adjusted_mode.crtc_clock;
> u32 divsel, phaseinc, auxdiv, phasedir = 0;
> u32 temp;
>
> @@ -5080,7 +5080,7 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
> static void ironlake_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
> enum pipe pch_transcoder)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> @@ -5123,7 +5123,7 @@ static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool e
>
> static void ivybridge_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> switch (crtc->pipe) {
> @@ -5153,7 +5153,7 @@ static struct intel_encoder *
> intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> const struct drm_connector_state *connector_state;
> const struct drm_connector *connector;
> struct intel_encoder *encoder = NULL;
> @@ -5185,7 +5185,7 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
> static void ironlake_pch_enable(const struct intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum pipe pipe = crtc->pipe;
> @@ -5239,7 +5239,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
> if (HAS_PCH_CPT(dev_priv) &&
> intel_crtc_has_dp_encoder(crtc_state)) {
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
> i915_reg_t reg = TRANS_DP_CTL(pipe);
> enum port port;
> @@ -5269,7 +5269,7 @@ static void ironlake_pch_enable(const struct intel_atomic_state *state,
> static void lpt_pch_enable(const struct intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> @@ -5386,10 +5386,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> struct intel_crtc_scaler_state *scaler_state =
> &crtc_state->scaler_state;
> struct intel_crtc *intel_crtc =
> - to_intel_crtc(crtc_state->base.crtc);
> + to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
>
> /*
> * Src coordinates are already rotated by 270 degrees for
> @@ -5405,7 +5405,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> * Once NV12 is enabled, handle it here while allocating scaler
> * for NV12.
> */
> - if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
> + if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
> need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
> return -EINVAL;
> @@ -5477,13 +5477,13 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> */
> int skl_update_scaler_crtc(struct intel_crtc_state *state)
> {
> - const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode;
> bool need_scaler = false;
>
> if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> need_scaler = true;
>
> - return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
> + return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX,
> &state->scaler_state.scaler_id,
> state->pipe_src_w, state->pipe_src_h,
> adjusted_mode->crtc_hdisplay,
> @@ -5583,7 +5583,7 @@ static void skylake_scaler_disable(struct intel_crtc *crtc)
>
> static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> const struct intel_crtc_scaler_state *scaler_state =
> @@ -5620,7 +5620,7 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
>
> static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -5641,7 +5641,7 @@ static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
>
> void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> @@ -5677,7 +5677,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
>
> void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> @@ -5787,7 +5787,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
> static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (!old_crtc_state->ips_enabled)
> @@ -5803,7 +5803,7 @@ static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_s
> * Disable IPS before we program the LUT.
> */
> if (IS_HASWELL(dev_priv) &&
> - (new_crtc_state->base.color_mgmt_changed ||
> + (new_crtc_state->uapi.color_mgmt_changed ||
> new_crtc_state->update_pipe) &&
> new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> return true;
> @@ -5814,7 +5814,7 @@ static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_s
> static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (!new_crtc_state->ips_enabled)
> @@ -5830,7 +5830,7 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
> * Re-enable IPS after the LUT has been programmed.
> */
> if (IS_HASWELL(dev_priv) &&
> - (new_crtc_state->base.color_mgmt_changed ||
> + (new_crtc_state->uapi.color_mgmt_changed ||
> new_crtc_state->update_pipe) &&
> new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
> return true;
> @@ -5840,7 +5840,7 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s
> * forcibly enable IPS on the first fastset.
> */
> if (new_crtc_state->update_pipe &&
> - old_crtc_state->base.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
> + old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
> return true;
>
> return !old_crtc_state->ips_enabled;
> @@ -5871,10 +5871,10 @@ static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
>
> static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct drm_atomic_state *state = old_crtc_state->base.state;
> + struct drm_atomic_state *state = old_crtc_state->uapi.state;
> struct intel_crtc_state *pipe_config =
> intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
> crtc);
> @@ -5884,7 +5884,7 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
>
> intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
>
> - if (pipe_config->update_wm_post && pipe_config->base.active)
> + if (pipe_config->update_wm_post && pipe_config->hw.active)
> intel_update_watermarks(crtc);
>
> if (hsw_post_update_enable_ips(old_crtc_state, pipe_config))
> @@ -5914,10 +5914,10 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
> static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> struct intel_crtc_state *pipe_config)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct drm_atomic_state *state = old_crtc_state->base.state;
> + struct drm_atomic_state *state = old_crtc_state->uapi.state;
> struct drm_plane *primary = crtc->base.primary;
> struct drm_plane_state *old_primary_state =
> drm_atomic_get_old_plane_state(state, primary);
> @@ -5962,7 +5962,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> * event which is after the vblank start event, so we need to have a
> * wait-for-vblank between disabling the plane and the pipe.
> */
> - if (HAS_GMCH(dev_priv) && old_crtc_state->base.active &&
> + if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
> pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
> intel_wait_for_vblank(dev_priv, crtc->pipe);
>
> @@ -5974,7 +5974,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
> * WaCxSRDisabledForSpriteScaling:ivb
> */
> if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) &&
> - old_crtc_state->base.active)
> + old_crtc_state->hw.active)
> intel_wait_for_vblank(dev_priv, crtc->pipe);
>
> /*
> @@ -6269,7 +6269,7 @@ static void intel_encoders_update_pipe(struct intel_crtc *crtc,
>
> static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_plane *plane = to_intel_plane(crtc->base.primary);
>
> plane->disable_plane(plane, crtc_state);
> @@ -6278,7 +6278,7 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
> static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->base.crtc;
> + struct drm_crtc *crtc = pipe_config->uapi.crtc;
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -6412,7 +6412,7 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->base.crtc;
> + struct drm_crtc *crtc = pipe_config->uapi.crtc;
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum pipe pipe = intel_crtc->pipe, hsw_workaround_pipe;
> @@ -6521,7 +6521,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>
> static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -6537,7 +6537,7 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = old_crtc_state->base.crtc;
> + struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -6596,7 +6596,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = old_crtc_state->base.crtc;
> + struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> @@ -6630,7 +6630,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
>
> static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (!crtc_state->gmch_pfit.control)
> @@ -6760,14 +6760,14 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
>
> static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct drm_encoder *encoder;
> enum pipe pipe = crtc->pipe;
> u64 mask;
> enum transcoder transcoder = crtc_state->cpu_transcoder;
>
> - if (!crtc_state->base.active)
> + if (!crtc_state->hw.active)
> return 0;
>
> mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
> @@ -6777,7 +6777,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
>
> drm_for_each_encoder_mask(encoder, &dev_priv->drm,
> - crtc_state->base.encoder_mask) {
> + crtc_state->uapi.encoder_mask) {
> struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
>
> mask |= BIT_ULL(intel_encoder->power_domain);
> @@ -6795,7 +6795,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> static u64
> modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum intel_display_power_domain domain;
> u64 domains, new_domains, old_domains;
> @@ -6824,7 +6824,7 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
> static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->base.crtc;
> + struct drm_crtc *crtc = pipe_config->uapi.crtc;
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -6880,7 +6880,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>
> static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0);
> @@ -6890,7 +6890,7 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
> static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = pipe_config->base.crtc;
> + struct drm_crtc *crtc = pipe_config->uapi.crtc;
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -6940,7 +6940,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>
> static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (!old_crtc_state->gmch_pfit.control)
> @@ -6956,7 +6956,7 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
> static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct intel_atomic_state *state)
> {
> - struct drm_crtc *crtc = old_crtc_state->base.crtc;
> + struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -7124,8 +7124,8 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
> if (!crtc_state)
> return;
>
> - I915_STATE_WARN(!crtc_state->base.active,
> - "connector is active, but attached crtc isn't\n");
> + I915_STATE_WARN(!crtc_state->hw.active,
> + "connector is active, but attached crtc isn't\n");
>
> if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
> return;
> @@ -7136,8 +7136,8 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
> I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
> "attached encoder crtc differs from connector crtc\n");
> } else {
> - I915_STATE_WARN(crtc_state && crtc_state->base.active,
> - "attached crtc is active, but connector isn't\n");
> + I915_STATE_WARN(crtc_state && crtc_state->hw.active,
> + "attached crtc is active, but connector isn't\n");
> I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
> "best encoder set without crtc!\n");
> }
> @@ -7145,7 +7145,7 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
>
> static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
> {
> - if (crtc_state->base.enable && crtc_state->has_pch_encoder)
> + if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
> return crtc_state->fdi_lanes;
>
> return 0;
> @@ -7155,7 +7155,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct drm_atomic_state *state = pipe_config->base.state;
> + struct drm_atomic_state *state = pipe_config->uapi.state;
> struct intel_crtc *other_crtc;
> struct intel_crtc_state *other_crtc_state;
>
> @@ -7228,7 +7228,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_device *dev = intel_crtc->base.dev;
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> int lane, link_bw, fdi_dotclock, ret;
> bool needs_recompute = false;
>
> @@ -7274,7 +7274,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
>
> bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> /* IPS only exists on ULT machines and is tied to pipe A. */
> @@ -7304,9 +7304,9 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv =
> - to_i915(crtc_state->base.crtc->dev);
> + to_i915(crtc_state->uapi.crtc->dev);
> struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(crtc_state->base.state);
> + to_intel_atomic_state(crtc_state->uapi.state);
>
> if (!hsw_crtc_state_ips_capable(crtc_state))
> return false;
> @@ -7345,7 +7345,7 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
> {
> u32 pixel_rate;
>
> - pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
> + pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
>
> /*
> * We only use IF-ID interlacing. If we ever use
> @@ -7378,12 +7378,12 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
>
> static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> if (HAS_GMCH(dev_priv))
> /* FIXME calculate proper pipe pixel rate for GMCH pfit */
> crtc_state->pixel_rate =
> - crtc_state->base.adjusted_mode.crtc_clock;
> + crtc_state->hw.adjusted_mode.crtc_clock;
> else
> crtc_state->pixel_rate =
> ilk_pipe_pixel_rate(crtc_state);
> @@ -7393,7 +7393,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> int clock_limit = dev_priv->max_dotclk_freq;
>
> if (INTEL_GEN(dev_priv) < 4) {
> @@ -7419,7 +7419,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>
> if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
> - pipe_config->base.ctm) {
> + pipe_config->hw.ctm) {
> /*
> * There is only one pipe CSC unit per pipe, and we need that
> * for output conversion from RGB->YCBCR. So if CTM is already
> @@ -7613,7 +7613,7 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
> static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
> const struct intel_link_m_n *m_n)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -7640,7 +7640,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
> const struct intel_link_m_n *m_n,
> const struct intel_link_m_n *m2_n2)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> enum transcoder transcoder = crtc_state->cpu_transcoder;
> @@ -7953,7 +7953,7 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
> if (!pipe_config)
> return -ENOMEM;
>
> - pipe_config->base.crtc = &crtc->base;
> + pipe_config->uapi.crtc = &crtc->base;
> pipe_config->pixel_multiplier = 1;
> pipe_config->dpll = *dpll;
>
> @@ -8113,11 +8113,11 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
>
> static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> - const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> u32 crtc_vtotal, crtc_vblank_end;
> int vsyncshift = 0;
>
> @@ -8175,7 +8175,7 @@ static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
>
> static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> @@ -8189,7 +8189,7 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
>
> static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> if (IS_GEN(dev_priv, 2))
> @@ -8211,39 +8211,39 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
> u32 tmp;
>
> tmp = I915_READ(HTOTAL(cpu_transcoder));
> - pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
> - pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
>
> if (!transcoder_is_dsi(cpu_transcoder)) {
> tmp = I915_READ(HBLANK(cpu_transcoder));
> - pipe_config->base.adjusted_mode.crtc_hblank_start =
> + pipe_config->hw.adjusted_mode.crtc_hblank_start =
> (tmp & 0xffff) + 1;
> - pipe_config->base.adjusted_mode.crtc_hblank_end =
> + pipe_config->hw.adjusted_mode.crtc_hblank_end =
> ((tmp >> 16) & 0xffff) + 1;
> }
> tmp = I915_READ(HSYNC(cpu_transcoder));
> - pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
> - pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
>
> tmp = I915_READ(VTOTAL(cpu_transcoder));
> - pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
> - pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
>
> if (!transcoder_is_dsi(cpu_transcoder)) {
> tmp = I915_READ(VBLANK(cpu_transcoder));
> - pipe_config->base.adjusted_mode.crtc_vblank_start =
> + pipe_config->hw.adjusted_mode.crtc_vblank_start =
> (tmp & 0xffff) + 1;
> - pipe_config->base.adjusted_mode.crtc_vblank_end =
> + pipe_config->hw.adjusted_mode.crtc_vblank_end =
> ((tmp >> 16) & 0xffff) + 1;
> }
> tmp = I915_READ(VSYNC(cpu_transcoder));
> - pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
> - pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
> + pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
>
> if (intel_pipe_is_interlaced(pipe_config)) {
> - pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
> - pipe_config->base.adjusted_mode.crtc_vtotal += 1;
> - pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
> + pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
> + pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
> + pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
> }
> }
>
> @@ -8258,27 +8258,27 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
> pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
> pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
>
> - pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
> - pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
> + pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
> + pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
> }
>
> void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> struct intel_crtc_state *pipe_config)
> {
> - mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
> - mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
> - mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
> - mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
> + mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> + mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
> + mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
> + mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
>
> - mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
> - mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
> - mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
> - mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
> + mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
> + mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
> + mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
> + mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
>
> - mode->flags = pipe_config->base.adjusted_mode.flags;
> + mode->flags = pipe_config->hw.adjusted_mode.flags;
> mode->type = DRM_MODE_TYPE_DRIVER;
>
> - mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
> + mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
>
> mode->hsync = drm_mode_hsync(mode);
> mode->vrefresh = drm_mode_vrefresh(mode);
> @@ -8287,7 +8287,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
>
> static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 pipeconf;
>
> @@ -8324,7 +8324,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> }
> }
>
> - if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> if (INTEL_GEN(dev_priv) < 4 ||
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
> pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
> @@ -8733,7 +8733,7 @@ bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
>
> static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> @@ -8856,7 +8856,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> * but in case the pipe is enabled w/o any ports we need a sane
> * default.
> */
> - pipe_config->base.adjusted_mode.crtc_clock =
> + pipe_config->hw.adjusted_mode.crtc_clock =
> pipe_config->port_clock / pipe_config->pixel_multiplier;
>
> ret = true;
> @@ -9371,7 +9371,7 @@ void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
>
> static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> u32 val;
> @@ -9399,7 +9399,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
> if (crtc_state->dither)
> val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
>
> - if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> val |= PIPECONF_INTERLACED_ILK;
> else
> val |= PIPECONF_PROGRESSIVE;
> @@ -9425,7 +9425,7 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
>
> static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> u32 val = 0;
> @@ -9433,7 +9433,7 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
> if (IS_HASWELL(dev_priv) && crtc_state->dither)
> val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
>
> - if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> val |= PIPECONF_INTERLACED_ILK;
> else
> val |= PIPECONF_PROGRESSIVE;
> @@ -9448,7 +9448,7 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
>
> static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 val = 0;
>
> @@ -9634,7 +9634,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_atomic_state *state =
> - to_intel_atomic_state(crtc_state->base.state);
> + to_intel_atomic_state(crtc_state->uapi.state);
> const struct intel_limit *limit;
> int refclk = 120000;
>
> @@ -10059,7 +10059,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_atomic_state *state =
> - to_intel_atomic_state(crtc_state->base.state);
> + to_intel_atomic_state(crtc_state->uapi.state);
>
> if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
> INTEL_GEN(dev_priv) >= 11) {
> @@ -10630,7 +10630,7 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
> }
>
> ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> - &crtc_state->base,
> + &crtc_state->uapi,
> DRM_PLANE_HELPER_NO_SCALING,
> DRM_PLANE_HELPER_NO_SCALING,
> true, true);
> @@ -10817,7 +10817,7 @@ i9xx_cursor_max_stride(struct intel_plane *plane,
>
> static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 cntl = 0;
>
> @@ -11229,12 +11229,12 @@ int intel_get_load_detect_pipe(struct drm_connector *connector,
> goto fail;
> }
>
> - crtc_state->base.active = crtc_state->base.enable = true;
> + crtc_state->uapi.active = crtc_state->uapi.enable = true;
>
> if (!mode)
> mode = &load_detect_mode;
>
> - ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
> + ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, mode);
> if (ret)
> goto fail;
>
> @@ -11442,7 +11442,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
> * we may need some idea for the dotclock anyway.
> * Calculate one based on the FDI configuration.
> */
> - pipe_config->base.adjusted_mode.crtc_clock =
> + pipe_config->hw.adjusted_mode.crtc_clock =
> intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
> &pipe_config->fdi_m_n);
> }
> @@ -11472,7 +11472,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
> return NULL;
> }
>
> - crtc_state->base.crtc = &crtc->base;
> + crtc_state->uapi.crtc = &crtc->base;
>
> if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
> kfree(crtc_state);
> @@ -11543,12 +11543,12 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
> const struct intel_plane_state *old_plane_state,
> struct intel_plane_state *plane_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> bool mode_changed = needs_modeset(crtc_state);
> - bool was_crtc_enabled = old_crtc_state->base.active;
> - bool is_crtc_enabled = crtc_state->base.active;
> + bool was_crtc_enabled = old_crtc_state->hw.active;
> + bool is_crtc_enabled = crtc_state->hw.active;
> bool turn_off, turn_on, visible, was_visible;
> int ret;
>
> @@ -11715,9 +11715,9 @@ static int icl_add_linked_planes(struct intel_atomic_state *state)
>
> static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state);
> + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> struct intel_plane *plane, *linked;
> struct intel_plane_state *plane_state;
> int i;
> @@ -11787,9 +11787,9 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
>
> static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct intel_atomic_state *state =
> - to_intel_atomic_state(new_crtc_state->base.state);
> + to_intel_atomic_state(new_crtc_state->uapi.state);
> const struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(state, crtc);
>
> @@ -11807,10 +11807,10 @@ static int intel_crtc_atomic_check(struct drm_crtc *_crtc,
> bool mode_changed = needs_modeset(crtc_state);
>
> if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
> - mode_changed && !crtc_state->base.active)
> + mode_changed && !crtc_state->hw.active)
> crtc_state->update_wm_post = true;
>
> - if (mode_changed && crtc_state->base.enable &&
> + if (mode_changed && crtc_state->hw.enable &&
> dev_priv->display.crtc_compute_clock &&
> !WARN_ON(crtc_state->shared_dpll)) {
> ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
> @@ -11823,10 +11823,10 @@ static int intel_crtc_atomic_check(struct drm_crtc *_crtc,
> * when C8 planes are getting enabled/disabled.
> */
> if (c8_planes_changed(crtc_state))
> - crtc_state->base.color_mgmt_changed = true;
> + crtc_state->uapi.color_mgmt_changed = true;
>
> if (mode_changed || crtc_state->update_pipe ||
> - crtc_state->base.color_mgmt_changed) {
> + crtc_state->uapi.color_mgmt_changed) {
> ret = intel_color_check(crtc_state);
> if (ret)
> return ret;
> @@ -11948,7 +11948,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct drm_atomic_state *state = pipe_config->base.state;
> + struct drm_atomic_state *state = pipe_config->uapi.state;
> struct drm_connector *connector;
> struct drm_connector_state *connector_state;
> int bpp, i;
> @@ -12101,7 +12101,7 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state,
> const char *context)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> const struct intel_plane_state *plane_state;
> struct intel_plane *plane;
> @@ -12110,14 +12110,14 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>
> DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n",
> crtc->base.base.id, crtc->base.name,
> - yesno(pipe_config->base.enable), context);
> + yesno(pipe_config->hw.enable), context);
>
> - if (!pipe_config->base.enable)
> + if (!pipe_config->hw.enable)
> goto dump_planes;
>
> snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
> DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n",
> - yesno(pipe_config->base.active),
> + yesno(pipe_config->hw.active),
> buf, pipe_config->output_types,
> output_formats(pipe_config->output_format));
>
> @@ -12157,10 +12157,10 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
> intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
>
> DRM_DEBUG_KMS("requested mode:\n");
> - drm_mode_debug_printmodeline(&pipe_config->base.mode);
> + drm_mode_debug_printmodeline(&pipe_config->hw.mode);
> DRM_DEBUG_KMS("adjusted mode:\n");
> - drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
> - intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
> + drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
> + intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode);
> DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
> pipe_config->port_clock,
> pipe_config->pipe_src_w, pipe_config->pipe_src_h,
> @@ -12278,7 +12278,7 @@ static int
> clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv =
> - to_i915(crtc_state->base.crtc->dev);
> + to_i915(crtc_state->uapi.crtc->dev);
> struct intel_crtc_state *saved_state;
>
> saved_state = kzalloc(sizeof(*saved_state), GFP_KERNEL);
> @@ -12301,9 +12301,10 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
> saved_state->wm = crtc_state->wm;
>
> /* Keep base drm_crtc_state intact, only clear our extended struct */
> - BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
> - memcpy(&crtc_state->base + 1, &saved_state->base + 1,
> - sizeof(*crtc_state) - sizeof(crtc_state->base));
> + BUILD_BUG_ON(offsetof(struct intel_crtc_state, uapi));
> + BUILD_BUG_ON(offsetof(struct intel_crtc_state, hw));
> + memcpy(&crtc_state->uapi + 1, &saved_state->uapi + 1,
> + sizeof(*crtc_state) - sizeof(crtc_state->uapi));
>
> kfree(saved_state);
> return 0;
> @@ -12312,8 +12313,8 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
> static int
> intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> {
> - struct drm_crtc *crtc = pipe_config->base.crtc;
> - struct drm_atomic_state *state = pipe_config->base.state;
> + struct drm_crtc *crtc = pipe_config->uapi.crtc;
> + struct drm_atomic_state *state = pipe_config->uapi.state;
> struct intel_encoder *encoder;
> struct drm_connector *connector;
> struct drm_connector_state *connector_state;
> @@ -12333,13 +12334,13 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> * positive or negative polarity is requested, treat this as meaning
> * negative polarity.
> */
> - if (!(pipe_config->base.adjusted_mode.flags &
> + if (!(pipe_config->hw.adjusted_mode.flags &
> (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
> - pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
> + pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
>
> - if (!(pipe_config->base.adjusted_mode.flags &
> + if (!(pipe_config->hw.adjusted_mode.flags &
> (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
> - pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
> + pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
>
> ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
> pipe_config);
> @@ -12356,7 +12357,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> * computation to clearly distinguish it from the adjusted mode, which
> * can be changed by the connectors in the below retry loop.
> */
> - drm_mode_get_hv_timing(&pipe_config->base.mode,
> + drm_mode_get_hv_timing(&pipe_config->hw.mode,
> &pipe_config->pipe_src_w,
> &pipe_config->pipe_src_h);
>
> @@ -12389,7 +12390,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> pipe_config->pixel_multiplier = 1;
>
> /* Fill in default crtc timings, allow encoders to overwrite them. */
> - drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
> + drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
> CRTC_STEREO_DOUBLE);
>
> /* Pass our mode to the connectors and the CRTC to give them a chance to
> @@ -12414,7 +12415,7 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> /* Set default port clock if not overwritten by the encoder. Needs to be
> * done afterwards in case the encoder adjusts the mode. */
> if (!pipe_config->port_clock)
> - pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
> + pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
> * pipe_config->pixel_multiplier;
>
> ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
> @@ -12458,7 +12459,7 @@ bool intel_fuzzy_clock_check(int clock1, int clock2)
>
> diff = abs(clock1 - clock2);
>
> - if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
> + if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 101)
> return true;
>
> return false;
> @@ -12578,12 +12579,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> const struct intel_crtc_state *pipe_config,
> bool fastset)
> {
> - struct drm_i915_private *dev_priv = to_i915(current_config->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
> bool ret = true;
> u32 bp_gamma = 0;
> bool fixup_inherited = fastset &&
> - (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
> - !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED);
> + (current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
> + !(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
>
> if (fixup_inherited && !fastboot_enabled(dev_priv)) {
> DRM_DEBUG_KMS("initial modeset and fastboot not set\n");
> @@ -12772,19 +12773,19 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>
> PIPE_CONF_CHECK_X(output_types);
>
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
>
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
>
> PIPE_CONF_CHECK_I(pixel_multiplier);
> PIPE_CONF_CHECK_I(output_format);
> @@ -12800,17 +12801,17 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>
> PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
>
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_INTERLACE);
>
> if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_PHSYNC);
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_NHSYNC);
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_PVSYNC);
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_NVSYNC);
> }
>
> @@ -12849,7 +12850,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>
> bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
> if (bp_gamma)
> - PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut, bp_gamma);
> + PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, uapi.gamma_lut, bp_gamma);
>
> }
>
> @@ -12894,7 +12895,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> PIPE_CONF_CHECK_I(pipe_bpp);
>
> - PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
> + PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
>
> PIPE_CONF_CHECK_I(min_voltage_level);
> @@ -12925,7 +12926,7 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
> if (pipe_config->has_pch_encoder) {
> int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
> &pipe_config->fdi_m_n);
> - int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
> + int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
>
> /*
> * FDI already provided one idea for the dotclock.
> @@ -12953,7 +12954,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
> const enum pipe pipe = crtc->pipe;
> int plane, level, max_level = ilk_wm_max_level(dev_priv);
>
> - if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
> + if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
> return;
>
> hw = kzalloc(sizeof(*hw), GFP_KERNEL);
> @@ -13162,12 +13163,12 @@ verify_crtc_state(struct intel_crtc *crtc,
> struct drm_atomic_state *state;
> bool active;
>
> - state = old_crtc_state->base.state;
> - __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->base);
> + state = old_crtc_state->uapi.state;
> + __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
> pipe_config = old_crtc_state;
> memset(pipe_config, 0, sizeof(*pipe_config));
> - pipe_config->base.crtc = &crtc->base;
> - pipe_config->base.state = state;
> + pipe_config->uapi.crtc = &crtc->base;
> + pipe_config->uapi.state = state;
>
> DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
>
> @@ -13175,23 +13176,26 @@ verify_crtc_state(struct intel_crtc *crtc,
>
> /* we keep both pipes enabled on 830 */
> if (IS_I830(dev_priv))
> - active = new_crtc_state->base.active;
> + active = new_crtc_state->hw.active;
>
> - I915_STATE_WARN(new_crtc_state->base.active != active,
> - "crtc active state doesn't match with hw state "
> - "(expected %i, found %i)\n", new_crtc_state->base.active, active);
> + I915_STATE_WARN(new_crtc_state->hw.active != active,
> + "crtc active state doesn't match with hw state "
> + "(expected %i, found %i)\n",
> + new_crtc_state->hw.active, active);
>
> - I915_STATE_WARN(crtc->active != new_crtc_state->base.active,
> - "transitional active state does not match atomic hw state "
> - "(expected %i, found %i)\n", new_crtc_state->base.active, crtc->active);
> + I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
> + "transitional active state does not match atomic hw state "
> + "(expected %i, found %i)\n",
> + new_crtc_state->hw.active, crtc->active);
>
> for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
> enum pipe pipe;
>
> active = encoder->get_hw_state(encoder, &pipe);
> - I915_STATE_WARN(active != new_crtc_state->base.active,
> - "[ENCODER:%i] active %i with crtc active %i\n",
> - encoder->base.base.id, active, new_crtc_state->base.active);
> + I915_STATE_WARN(active != new_crtc_state->hw.active,
> + "[ENCODER:%i] active %i with crtc active %i\n",
> + encoder->base.base.id, active,
> + new_crtc_state->hw.active);
>
> I915_STATE_WARN(active && crtc->pipe != pipe,
> "Encoder connected to wrong pipe %c\n",
> @@ -13203,7 +13207,7 @@ verify_crtc_state(struct intel_crtc *crtc,
>
> intel_crtc_compute_pixel_rate(pipe_config);
>
> - if (!new_crtc_state->base.active)
> + if (!new_crtc_state->hw.active)
> return;
>
> intel_pipe_config_sanity_check(dev_priv, pipe_config);
> @@ -13265,7 +13269,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
>
> crtc_mask = drm_crtc_mask(&crtc->base);
>
> - if (new_crtc_state->base.active)
> + if (new_crtc_state->hw.active)
> I915_STATE_WARN(!(pll->active_mask & crtc_mask),
> "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
> pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
> @@ -13343,7 +13347,7 @@ intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
>
> static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> /*
> @@ -13374,7 +13378,7 @@ static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
> * answer that's slightly in the future.
> */
> if (IS_GEN(dev_priv, 2)) {
> - const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> int vtotal;
>
> vtotal = adjusted_mode->crtc_vtotal;
> @@ -13424,7 +13428,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
>
> /* look at all crtc's that are going to be enabled in during modeset */
> for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> - if (!crtc_state->base.active ||
> + if (!crtc_state->hw.active ||
> !needs_modeset(crtc_state))
> continue;
>
> @@ -13449,7 +13453,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state)
>
> crtc_state->hsw_workaround_pipe = INVALID_PIPE;
>
> - if (!crtc_state->base.active ||
> + if (!crtc_state->hw.active ||
> needs_modeset(crtc_state))
> continue;
>
> @@ -13492,12 +13496,12 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> - if (new_crtc_state->base.active)
> + if (new_crtc_state->hw.active)
> state->active_pipes |= BIT(crtc->pipe);
> else
> state->active_pipes &= ~BIT(crtc->pipe);
>
> - if (old_crtc_state->base.active != new_crtc_state->base.active)
> + if (old_crtc_state->hw.active != new_crtc_state->hw.active)
> state->active_pipe_changes |= BIT(crtc->pipe);
> }
>
> @@ -13536,7 +13540,7 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
> return;
>
> - new_crtc_state->base.mode_changed = false;
> + new_crtc_state->uapi.mode_changed = false;
> new_crtc_state->update_pipe = true;
>
> /*
> @@ -13571,9 +13575,9 @@ static int intel_atomic_check(struct drm_device *dev,
> /* Catch I915_MODE_FLAG_INHERITED */
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> - if (new_crtc_state->base.mode.private_flags !=
> - old_crtc_state->base.mode.private_flags)
> - new_crtc_state->base.mode_changed = true;
> + if (new_crtc_state->hw.mode.private_flags !=
> + old_crtc_state->hw.mode.private_flags)
> + new_crtc_state->uapi.mode_changed = true;
> }
>
> ret = drm_atomic_helper_check_modeset(dev, &state->base);
> @@ -13585,7 +13589,7 @@ static int intel_atomic_check(struct drm_device *dev,
> if (!needs_modeset(new_crtc_state))
> continue;
>
> - if (!new_crtc_state->base.enable) {
> + if (!new_crtc_state->uapi.enable) {
> any_ms = true;
> continue;
> }
> @@ -13693,11 +13697,11 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
> static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
> - crtc->base.mode = new_crtc_state->base.mode;
> + crtc->base.mode = new_crtc_state->hw.mode;
>
> /*
> * Update pipe size and adjust fitter if needed: the reason for this is
> @@ -13738,7 +13742,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
> * CRTC was enabled.
> */
> if (!modeset) {
> - if (new_crtc_state->base.color_mgmt_changed ||
> + if (new_crtc_state->uapi.color_mgmt_changed ||
> new_crtc_state->update_pipe)
> intel_color_commit(new_crtc_state);
>
> @@ -13805,7 +13809,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
> * of enabling them on the CRTC's first fastset.
> */
> if (new_crtc_state->update_pipe && !modeset &&
> - old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
> + old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
> intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
> }
>
> @@ -13837,11 +13841,10 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> intel_check_pch_fifo_underruns(dev_priv);
>
> /* FIXME unify this for all platforms */
> - if (!new_crtc_state->base.active &&
> + if (!new_crtc_state->hw.active &&
> !HAS_GMCH(dev_priv) &&
> dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state,
> - new_crtc_state);
> + dev_priv->display.initial_watermarks(state, new_crtc_state);
> }
>
> static void intel_commit_modeset_disables(struct intel_atomic_state *state)
> @@ -13864,7 +13867,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
>
> intel_pre_plane_update(old_crtc_state, new_crtc_state);
>
> - if (old_crtc_state->base.active)
> + if (old_crtc_state->hw.active)
> intel_old_crtc_state_disables(state,
> old_crtc_state,
> new_crtc_state,
> @@ -13879,7 +13882,7 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state)
> int i;
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> - if (!new_crtc_state->base.active)
> + if (!new_crtc_state->hw.active)
> continue;
>
> intel_update_crtc(crtc, state, old_crtc_state,
> @@ -13902,7 +13905,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
> /* ignore allocations for crtc's that have been turned off. */
> - if (new_crtc_state->base.active)
> + if (new_crtc_state->hw.active)
> entries[i] = old_crtc_state->wm.skl.ddb;
>
> /* If 2nd DBuf slice required, enable it here */
> @@ -13924,7 +13927,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
>
> pipe = crtc->pipe;
>
> - if (updated & cmask || !new_crtc_state->base.active)
> + if (updated & cmask || !new_crtc_state->hw.active)
> continue;
>
> if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
> @@ -13943,7 +13946,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> */
> if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
> &old_crtc_state->wm.skl.ddb) &&
> - !new_crtc_state->base.active_changed &&
> + !new_crtc_state->uapi.active_changed &&
> state->wm_results.dirty_pipes != updated)
> vbl_wait = true;
>
> @@ -14076,12 +14079,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> bool modeset = needs_modeset(new_crtc_state);
>
> /* Complete events for now disable pipes here. */
> - if (modeset && !new_crtc_state->base.active && new_crtc_state->base.event) {
> + if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
> spin_lock_irq(&dev->event_lock);
> - drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->base.event);
> + drm_crtc_send_vblank_event(&crtc->base,
> + new_crtc_state->uapi.event);
> spin_unlock_irq(&dev->event_lock);
>
> - new_crtc_state->base.event = NULL;
> + new_crtc_state->uapi.event = NULL;
> }
> }
>
> @@ -14112,9 +14116,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> - if (new_crtc_state->base.active &&
> + if (new_crtc_state->hw.active &&
> !needs_modeset(new_crtc_state) &&
> - (new_crtc_state->base.color_mgmt_changed ||
> + (new_crtc_state->uapi.color_mgmt_changed ||
> new_crtc_state->update_pipe))
> intel_color_load_luts(new_crtc_state);
> }
> @@ -14573,16 +14577,16 @@ int
> skl_max_scale(const struct intel_crtc_state *crtc_state,
> const struct drm_format_info *format)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> int max_scale;
> int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
>
> - if (!crtc_state->base.enable)
> + if (!crtc_state->hw.enable)
> return DRM_PLANE_HELPER_NO_SCALING;
>
> - crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
> - max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
> + crtc_clock = crtc_state->hw.adjusted_mode.crtc_clock;
> + max_dotclk = to_intel_atomic_state(crtc_state->uapi.state)->cdclk.logical.cdclk;
>
> if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> max_dotclk *= 2;
> @@ -14715,7 +14719,7 @@ intel_legacy_cursor_update(struct drm_plane *plane,
> * When crtc is inactive or there is a modeset pending,
> * wait for it to complete in the slowpath
> */
> - if (!crtc_state->base.active || needs_modeset(crtc_state) ||
> + if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
> crtc_state->update_pipe)
> goto slow;
>
> @@ -14809,7 +14813,7 @@ intel_legacy_cursor_update(struct drm_plane *plane,
> mutex_unlock(&dev_priv->drm.struct_mutex);
> out_free:
> if (new_crtc_state)
> - intel_crtc_destroy_state(crtc, &new_crtc_state->base);
> + intel_crtc_destroy_state(crtc, &new_crtc_state->uapi);
> if (ret)
> intel_plane_destroy_state(plane, new_plane_state);
> else
> @@ -15135,7 +15139,7 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
> ret = -ENOMEM;
> goto fail;
> }
> - __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->base);
> + __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->uapi);
> intel_crtc->config = crtc_state;
>
> primary = intel_primary_plane_create(dev_priv, pipe);
> @@ -16490,7 +16494,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
> I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
> }
>
> - if (crtc_state->base.active) {
> + if (crtc_state->hw.active) {
> struct intel_plane *plane;
>
> /* Disable everything but the primary plane */
> @@ -16515,10 +16519,10 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
>
> /* Adjust the state of the output pipe according to whether we
> * have active connectors/encoders. */
> - if (crtc_state->base.active && !intel_crtc_has_encoders(crtc))
> + if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
> intel_crtc_disable_noatomic(&crtc->base, ctx);
>
> - if (crtc_state->base.active || HAS_GMCH(dev_priv)) {
> + if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
> /*
> * We start out with underrun reporting disabled to avoid races.
> * For correct bookkeeping mark this on active crtcs.
> @@ -16549,7 +16553,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
>
> static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> /*
> * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
> @@ -16562,7 +16566,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
> * road.
> */
> return IS_GEN(dev_priv, 6) &&
> - crtc_state->base.active &&
> + crtc_state->hw.active &&
> crtc_state->shared_dpll &&
> crtc_state->port_clock == 0;
> }
> @@ -16579,7 +16583,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
> * encoder is active and trying to read from a pipe) and the
> * pipe itself being active. */
> bool has_active_crtc = crtc_state &&
> - crtc_state->base.active;
> + crtc_state->hw.active;
>
> if (crtc_state && has_bogus_dpll_config(crtc_state)) {
> DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n",
> @@ -16683,22 +16687,22 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
>
> - __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
> + __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
> memset(crtc_state, 0, sizeof(*crtc_state));
> - __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->base);
> + __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->uapi);
>
> - crtc_state->base.active = crtc_state->base.enable =
> + crtc_state->hw.active = crtc_state->hw.enable =
> dev_priv->display.get_pipe_config(crtc, crtc_state);
>
> - crtc->base.enabled = crtc_state->base.enable;
> - crtc->active = crtc_state->base.active;
> + crtc->base.enabled = crtc_state->hw.enable;
> + crtc->active = crtc_state->hw.active;
>
> - if (crtc_state->base.active)
> + if (crtc_state->hw.active)
> dev_priv->active_pipes |= BIT(crtc->pipe);
>
> DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
> crtc->base.base.id, crtc->base.name,
> - enableddisabled(crtc_state->base.active));
> + enableddisabled(crtc_state->hw.active));
> }
>
> readout_plane_state(dev_priv);
> @@ -16720,7 +16724,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
>
> - if (crtc_state->base.active &&
> + if (crtc_state->hw.active &&
> crtc_state->shared_dpll == pll)
> pll->state.crtc_mask |= 1 << crtc->pipe;
> }
> @@ -16754,21 +16758,24 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> drm_connector_list_iter_begin(dev, &conn_iter);
> for_each_intel_connector_iter(connector, &conn_iter) {
> if (connector->get_hw_state(connector)) {
> - connector->base.dpms = DRM_MODE_DPMS_ON;
> + struct intel_crtc_state *crtc_state = NULL;
>
> + connector->base.dpms = DRM_MODE_DPMS_ON;
> encoder = connector->encoder;
> connector->base.encoder = &encoder->base;
>
> - if (encoder->base.crtc &&
> - encoder->base.crtc->state->active) {
> + if (encoder->base.crtc)
> + crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
> +
> + if (crtc_state && crtc_state->hw.active) {
> /*
> * This has to be done during hardware readout
> * because anything calling .crtc_disable may
> * rely on the connector_mask being accurate.
> */
> - encoder->base.crtc->state->connector_mask |=
> + crtc_state->uapi.connector_mask |=
> drm_connector_mask(&connector->base);
> - encoder->base.crtc->state->encoder_mask |=
> + crtc_state->uapi.encoder_mask |=
> drm_encoder_mask(&encoder->base);
> }
>
> @@ -16791,11 +16798,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> int min_cdclk = 0;
>
> memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
> - if (crtc_state->base.active) {
> + if (crtc_state->hw.active) {
> intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
> crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
> crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
> - intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
> + intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
> + crtc_state);
> WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
>
> /*
> @@ -16807,7 +16815,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> * set a flag to indicate that a full recalculation is
> * needed on the next commit.
> */
> - crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
> + crtc_state->hw.mode.private_flags = I915_MODE_FLAG_INHERITED;
>
> intel_crtc_compute_pixel_rate(crtc_state);
>
> @@ -16818,7 +16826,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> }
>
> drm_calc_timestamping_constants(&crtc->base,
> - &crtc_state->base.adjusted_mode);
> + &crtc_state->hw.adjusted_mode);
> update_scanline_offset(crtc_state);
> }
>
> @@ -16989,7 +16997,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
>
> drm_crtc_vblank_reset(&crtc->base);
>
> - if (crtc_state->base.active)
> + if (crtc_state->hw.active)
> intel_crtc_vblank_on(crtc_state);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index bc2cf4bec0e8..44a1c331d6b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -443,10 +443,10 @@ enum phy_fia {
> #define intel_atomic_crtc_state_for_each_plane_state( \
> plane, plane_state, \
> crtc_state) \
> - for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \
> - ((crtc_state)->base.plane_mask)) \
> + for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
> + ((crtc_state)->uapi.plane_mask)) \
> for_each_if ((plane_state = \
> - to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state, &plane->base))))
> + to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
>
> void intel_link_compute_m_n(u16 bpp, int nlanes,
> int pixel_clock, int link_clock,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 526423437f63..0ee69e8f0942 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -749,7 +749,31 @@ enum intel_output_format {
> };
>
> struct intel_crtc_state {
> - struct drm_crtc_state base;
> + union {
> + /*
> + * uapi (drm) state. This is the software state shown to userspace.
> + * In particular, the following members are used for bookkeeping:
> + * - crtc
> + * - state
> + * - *_changed
> + * - event
> + * - commit
> + * - mode_blob
> + */
> + struct drm_crtc_state uapi;
> +
> + /*
> + * actual hardware state, the state we program to the hardware.
> + * The following members are used to verify the hardware state:
> + * - enable
> + * - active
> + * - mode / adjusted_mode
> + * - color property blobs.
> + *
> + * During initial hw readout, they need to be copied to uapi.
> + */
> + struct drm_crtc_state hw;
> + };
>
> /**
> * quirks - bitfield with hw state readout quirks
> @@ -1093,7 +1117,7 @@ struct cxsr_latency {
>
> #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
> #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
> -#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
> +#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
> #define to_intel_connector(x) container_of(x, struct intel_connector, base)
> #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
> #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1aa39e92f0df..4297738655c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1967,7 +1967,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> struct intel_crtc_state *pipe_config,
> const struct link_config_limits *limits)
> {
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> int bpp, clock, lane_count;
> int mode_rate, link_clock, link_avail;
>
> @@ -2021,7 +2021,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> u8 dsc_max_bpc;
> int pipe_bpp;
> int ret;
> @@ -2132,7 +2132,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state)
> {
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct link_config_limits limits;
> int common_len;
> @@ -2220,8 +2220,8 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
> {
> const struct drm_display_info *info = &connector->display_info;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + &crtc_state->hw.adjusted_mode;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> int ret;
>
> if (!drm_mode_is_420_only(info, adjusted_mode) ||
> @@ -2249,7 +2249,7 @@ bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
> const struct intel_digital_connector_state *intel_conn_state =
> to_intel_digital_connector_state(conn_state);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
>
> /*
> * Our YCbCr output is always limited range.
> @@ -2282,11 +2282,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
> enum port port = encoder->port;
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_connector *intel_connector = intel_dp->attached_connector;
> struct intel_digital_connector_state *intel_conn_state =
> to_intel_digital_connector_state(conn_state);
> @@ -2400,8 +2400,8 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> enum port port = encoder->port;
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>
> intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
> pipe_config->lane_count,
> @@ -2998,7 +2998,7 @@ static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
> static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
> const struct intel_crtc_state *pipe_config)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> assert_pipe_disabled(dev_priv, crtc->pipe);
> @@ -3038,7 +3038,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
> static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
> const struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> assert_pipe_disabled(dev_priv, crtc->pipe);
> @@ -3198,7 +3198,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> u32 tmp, flags = 0;
> enum port port = encoder->port;
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>
> if (encoder->type == INTEL_OUTPUT_EDP)
> pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
> @@ -3233,7 +3233,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> flags |= DRM_MODE_FLAG_NVSYNC;
> }
>
> - pipe_config->base.adjusted_mode.flags |= flags;
> + pipe_config->hw.adjusted_mode.flags |= flags;
>
> if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
> pipe_config->limited_color_range = true;
> @@ -3250,7 +3250,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
> pipe_config->port_clock = 270000;
> }
>
> - pipe_config->base.adjusted_mode.crtc_clock =
> + pipe_config->hw.adjusted_mode.crtc_clock =
> intel_dotclock_calculate(pipe_config->port_clock,
> &pipe_config->dp_m_n);
>
> @@ -3465,7 +3465,7 @@ static void intel_enable_dp(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> u32 dp_reg = I915_READ(intel_dp->output_reg);
> enum pipe pipe = crtc->pipe;
> intel_wakeref_t wakeref;
> @@ -3598,7 +3598,7 @@ static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> lockdep_assert_held(&dev_priv->pps_mutex);
>
> @@ -4120,7 +4120,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> enum port port = encoder->port;
> u32 DP = intel_dp->DP;
>
> @@ -4881,7 +4881,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
>
> WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
>
> - if (!crtc_state->base.active)
> + if (!crtc_state->hw.active)
> return 0;
>
> if (conn_state->commit &&
> @@ -6700,7 +6700,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
> int refresh_rate)
> {
> struct intel_dp *intel_dp = dev_priv->drrs.dp;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
>
> if (refresh_rate <= 0) {
> @@ -6733,7 +6733,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
> return;
> }
>
> - if (!crtc_state->base.active) {
> + if (!crtc_state->hw.active) {
> DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
> return;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 2203be28ea01..cecb7ba5b482 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -42,13 +42,13 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> struct drm_connector_state *conn_state,
> struct link_config_limits *limits)
> {
> - struct drm_atomic_state *state = crtc_state->base.state;
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
> struct intel_dp *intel_dp = &intel_mst->primary->dp;
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> void *port = connector->port;
> bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
> DP_DPCD_QUIRK_CONSTANT_N);
> @@ -99,7 +99,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> struct intel_digital_connector_state *intel_conn_state =
> to_intel_digital_connector_state(conn_state);
> const struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
> void *port = connector->port;
> struct link_config_limits limits;
> int ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 556d1b30f06a..704f38681c4b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -739,7 +739,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
> u32 val;
>
> @@ -783,7 +783,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
> {
> struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum dpio_channel ch = vlv_dport_to_channel(dport);
> enum pipe pipe = crtc->pipe;
> unsigned int lane_mask =
> @@ -864,7 +864,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum dpio_channel ch = vlv_dport_to_channel(dport);
> enum pipe pipe = crtc->pipe;
> int data, i, stagger;
> @@ -953,7 +953,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
> const struct intel_crtc_state *old_crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe;
> + enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;
> u32 val;
>
> vlv_dpio_get(dev_priv);
> @@ -1016,7 +1016,7 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
> {
> struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum dpio_channel port = vlv_dport_to_channel(dport);
> enum pipe pipe = crtc->pipe;
>
> @@ -1046,7 +1046,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum dpio_channel port = vlv_dport_to_channel(dport);
> enum pipe pipe = crtc->pipe;
> u32 val;
> @@ -1075,7 +1075,7 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
> {
> struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> enum dpio_channel port = vlv_dport_to_channel(dport);
> enum pipe pipe = crtc->pipe;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 5e9e84c94a15..c2603aa56767 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -136,7 +136,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
> */
> void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>
> @@ -163,7 +163,7 @@ void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
> */
> void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
> @@ -208,7 +208,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
> */
> void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
> @@ -825,7 +825,7 @@ hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state,
> static struct intel_shared_dpll *
> hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> struct intel_shared_dpll *pll;
> enum intel_dpll_id pll_id;
> int clock = crtc_state->port_clock;
> @@ -1734,7 +1734,7 @@ static bool
> bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
> struct bxt_clk_div *clk_div)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct dpll best_clock;
>
> /* Calculate HDMI div */
> @@ -2257,7 +2257,7 @@ static bool
> cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
> struct skl_wrpll_params *wrpll_params)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> u32 afe_clock = crtc_state->port_clock * 5;
> u32 ref_clock;
> u32 dco_min = 7998000;
> @@ -2535,7 +2535,7 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
> static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
> struct skl_wrpll_params *pll_params)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> const struct icl_combo_pll_params *params =
> dev_priv->cdclk.hw.ref == 24000 ?
> icl_dp_combo_pll_24MHz_values :
> @@ -2557,7 +2557,7 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
> static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> struct skl_wrpll_params *pll_params)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> if (INTEL_GEN(dev_priv) >= 12) {
> switch (dev_priv->cdclk.hw.ref) {
> @@ -2594,7 +2594,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder,
> struct intel_dpll_hw_state *pll_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> u32 cfgcr0, cfgcr1;
> struct skl_wrpll_params pll_params = { 0 };
> bool ret;
> @@ -2726,7 +2726,7 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
> static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> struct intel_dpll_hw_state *pll_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int refclk_khz = dev_priv->cdclk.hw.ref;
> int clock = crtc_state->port_clock;
> u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index 9827f99491d1..28770c5765ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -178,9 +178,9 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
> else
> flags |= DRM_MODE_FLAG_NVSYNC;
>
> - pipe_config->base.adjusted_mode.flags |= flags;
> + pipe_config->hw.adjusted_mode.flags |= flags;
>
> - pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
> + pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
> }
>
> static void intel_disable_dvo(struct intel_encoder *encoder,
> @@ -207,8 +207,8 @@ static void intel_enable_dvo(struct intel_encoder *encoder,
> u32 temp = I915_READ(dvo_reg);
>
> intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
> - &pipe_config->base.mode,
> - &pipe_config->base.adjusted_mode);
> + &pipe_config->hw.mode,
> + &pipe_config->hw.adjusted_mode);
>
> I915_WRITE(dvo_reg, temp | DVO_ENABLE);
> I915_READ(dvo_reg);
> @@ -253,7 +253,7 @@ static int intel_dvo_compute_config(struct intel_encoder *encoder,
> struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> const struct drm_display_mode *fixed_mode =
> intel_dvo->attached_connector->panel.fixed_mode;
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>
> /*
> * If we have timings from the BIOS for the panel, put them in
> @@ -277,8 +277,8 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> enum pipe pipe = crtc->pipe;
> u32 dvo_val;
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 3111ecaeabd0..c6cc3775f3b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -667,7 +667,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> cache->vma = NULL;
> cache->flags = 0;
>
> - cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
> + cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 0a6846c5ba95..fd75016bd1e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -279,7 +279,7 @@ static void ibx_write_infoframe(struct intel_encoder *encoder,
> {
> const u32 *data = frame;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> u32 val = I915_READ(reg);
> int i;
> @@ -315,7 +315,7 @@ static void ibx_read_infoframe(struct intel_encoder *encoder,
> void *frame, ssize_t len)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> u32 val, *data = frame;
> int i;
>
> @@ -334,7 +334,7 @@ static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
> + enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
> i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
> u32 val = I915_READ(reg);
>
> @@ -356,7 +356,7 @@ static void cpt_write_infoframe(struct intel_encoder *encoder,
> {
> const u32 *data = frame;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> u32 val = I915_READ(reg);
> int i;
> @@ -395,7 +395,7 @@ static void cpt_read_infoframe(struct intel_encoder *encoder,
> void *frame, ssize_t len)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> u32 val, *data = frame;
> int i;
>
> @@ -414,7 +414,7 @@ static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
> + enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
> u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
>
> if ((val & VIDEO_DIP_ENABLE) == 0)
> @@ -432,7 +432,7 @@ static void vlv_write_infoframe(struct intel_encoder *encoder,
> {
> const u32 *data = frame;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
> u32 val = I915_READ(reg);
> int i;
> @@ -468,7 +468,7 @@ static void vlv_read_infoframe(struct intel_encoder *encoder,
> void *frame, ssize_t len)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> u32 val, *data = frame;
> int i;
>
> @@ -487,7 +487,7 @@ static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
> + enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
> u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
>
> if ((val & VIDEO_DIP_ENABLE) == 0)
> @@ -700,7 +700,7 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
> {
> struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> struct drm_connector *connector = conn_state->connector;
> int ret;
>
> @@ -796,7 +796,7 @@ intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
>
> ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
> conn_state->connector,
> - &crtc_state->base.adjusted_mode);
> + &crtc_state->hw.adjusted_mode);
> if (WARN_ON(ret))
> return false;
>
> @@ -957,7 +957,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> i915_reg_t reg;
>
> if ((crtc_state->infoframes.enable &
> @@ -982,7 +982,7 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> i915_reg_t reg;
>
> if ((crtc_state->infoframes.enable &
> @@ -1019,7 +1019,7 @@ static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
>
> /* Enable default_phase whenever the display mode is suitably aligned */
> if (gcp_default_phase_possible(crtc_state->pipe_bpp,
> - &crtc_state->base.adjusted_mode))
> + &crtc_state->hw.adjusted_mode))
> crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
> }
>
> @@ -1029,7 +1029,7 @@ static void ibx_set_infoframes(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
> struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
> i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> @@ -1088,7 +1088,7 @@ static void cpt_set_infoframes(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
> u32 val = I915_READ(reg);
> @@ -1137,7 +1137,7 @@ static void vlv_set_infoframes(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
> u32 val = I915_READ(reg);
> @@ -1733,9 +1733,9 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder,
> {
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> - const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> u32 hdmi_val;
>
> intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
> @@ -1826,7 +1826,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
> tmp & HDMI_COLOR_RANGE_16_235)
> pipe_config->limited_color_range = true;
>
> - pipe_config->base.adjusted_mode.flags |= flags;
> + pipe_config->hw.adjusted_mode.flags |= flags;
>
> if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
> dotclock = pipe_config->port_clock * 2 / 3;
> @@ -1836,7 +1836,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
> if (pipe_config->pixel_multiplier)
> dotclock /= pipe_config->pixel_multiplier;
>
> - pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> + pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
>
> pipe_config->lane_count = 4;
>
> @@ -1857,7 +1857,7 @@ static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config,
> const struct drm_connector_state *conn_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>
> WARN_ON(!pipe_config->has_hdmi_sink);
> DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
> @@ -1943,7 +1943,7 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder,
> {
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> enum pipe pipe = crtc->pipe;
> u32 temp;
> @@ -2007,7 +2007,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder,
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> struct intel_digital_port *intel_dig_port =
> hdmi_to_dig_port(intel_hdmi);
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> u32 temp;
>
> temp = I915_READ(intel_hdmi->hdmi_reg);
> @@ -2207,12 +2207,12 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
> int bpc)
> {
> struct drm_i915_private *dev_priv =
> - to_i915(crtc_state->base.crtc->dev);
> - struct drm_atomic_state *state = crtc_state->base.state;
> + to_i915(crtc_state->uapi.crtc->dev);
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> struct drm_connector_state *connector_state;
> struct drm_connector *connector;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> int i;
>
> if (HAS_GMCH(dev_priv))
> @@ -2237,7 +2237,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
> for_each_new_connector_in_state(state, connector, connector_state, i) {
> const struct drm_display_info *info = &connector->display_info;
>
> - if (connector_state->crtc != crtc_state->base.crtc)
> + if (connector_state->crtc != crtc_state->uapi.crtc)
> continue;
>
> if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
> @@ -2278,7 +2278,7 @@ static bool
> intel_hdmi_ycbcr420_config(struct drm_connector *connector,
> struct intel_crtc_state *config)
> {
> - struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(config->uapi.crtc);
>
> if (!connector->ycbcr_420_allowed) {
> DRM_ERROR("Platform doesn't support YCBCR420 output\n");
> @@ -2333,7 +2333,7 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
> {
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> int bpc, clock = adjusted_mode->crtc_clock;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> @@ -2375,7 +2375,7 @@ static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_s
> const struct intel_digital_connector_state *intel_conn_state =
> to_intel_digital_connector_state(conn_state);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
>
> /*
> * Our YCbCr output is always limited range.
> @@ -2403,7 +2403,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
> {
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> struct drm_connector *connector = conn_state->connector;
> struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
> struct intel_digital_connector_state *intel_conn_state =
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index f8f1308643a9..5145ff8b962b 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -189,7 +189,7 @@ void lspcon_ycbcr420_config(struct drm_connector *connector,
> {
> const struct drm_display_info *info = &connector->display_info;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
>
> if (drm_mode_is_420_only(info, adjusted_mode) &&
> connector->ycbcr_420_allowed) {
> @@ -475,7 +475,7 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> struct intel_lspcon *lspcon = &dig_port->lspcon;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
>
> if (!lspcon->active) {
> DRM_ERROR("Writing infoframes while LSPCON disabled ?\n");
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index 13841d7c455b..ca4ebb0f2230 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -135,7 +135,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
> else
> flags |= DRM_MODE_FLAG_PVSYNC;
>
> - pipe_config->base.adjusted_mode.flags |= flags;
> + pipe_config->hw.adjusted_mode.flags |= flags;
>
> if (INTEL_GEN(dev_priv) < 5)
> pipe_config->gmch_pfit.lvds_border_bits =
> @@ -148,7 +148,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
> pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
> }
>
> - pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
> + pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
> }
>
> static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
> @@ -230,8 +230,8 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder,
> {
> struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> enum pipe pipe = crtc->pipe;
> u32 temp;
>
> @@ -392,8 +392,8 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
> to_lvds_encoder(&intel_encoder->base);
> struct intel_connector *intel_connector =
> lvds_encoder->attached_connector;
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> unsigned int lvds_bpp;
>
> /* Should never happen!! */
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
> index bc14e9c0285a..6f3eaae3761f 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -178,7 +178,7 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
> struct intel_crtc_state *pipe_config,
> int fitting_mode)
> {
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> int x = 0, y = 0, width = 0, height = 0;
>
> /* Native modes don't need fitting */
> @@ -300,7 +300,7 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
> static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
> u32 *pfit_control)
> {
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> u32 scaled_width = adjusted_mode->crtc_hdisplay *
> pipe_config->pipe_src_h;
> u32 scaled_height = pipe_config->pipe_src_w *
> @@ -321,7 +321,7 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
> u32 *pfit_control, u32 *pfit_pgm_ratios,
> u32 *border)
> {
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> u32 scaled_width = adjusted_mode->crtc_hdisplay *
> pipe_config->pipe_src_h;
> u32 scaled_height = pipe_config->pipe_src_w *
> @@ -380,7 +380,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
> {
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>
> /* Native modes don't need fitting */
> if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
> @@ -1047,7 +1047,7 @@ static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state,
> struct intel_connector *connector = to_intel_connector(conn_state->connector);
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_panel *panel = &connector->panel;
> - enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> u32 ctl, ctl2;
>
> ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
> @@ -1077,7 +1077,7 @@ static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state,
> struct intel_connector *connector = to_intel_connector(conn_state->connector);
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_panel *panel = &connector->panel;
> - enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> u32 pwm_ctl, val;
>
> /* Controller 1 uses the utility pin. */
> @@ -1189,7 +1189,7 @@ void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
> struct intel_connector *connector = to_intel_connector(conn_state->connector);
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_panel *panel = &connector->panel;
> - enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>
> if (!panel->backlight.present)
> return;
> diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> index 6260a2082719..2746512f4466 100644
> --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> @@ -309,13 +309,13 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
> goto put_state;
> }
>
> - pipe_config->base.mode_changed = pipe_config->has_psr;
> + pipe_config->uapi.mode_changed = pipe_config->has_psr;
> pipe_config->crc_enabled = enable;
>
> if (IS_HASWELL(dev_priv) &&
> - pipe_config->base.active && crtc->pipe == PIPE_A &&
> + pipe_config->hw.active && crtc->pipe == PIPE_A &&
> pipe_config->cpu_transcoder == TRANSCODER_EDP)
> - pipe_config->base.mode_changed = true;
> + pipe_config->uapi.mode_changed = true;
>
> ret = drm_atomic_commit(state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index b3c7eef53bf3..8988dbe8c19e 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -538,8 +538,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
> - int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
> + int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> + int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
> int psr_max_h = 0, psr_max_v = 0;
>
> if (!dev_priv->psr.sink_psr2_support)
> @@ -605,7 +605,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> int psr_setup_time;
>
> if (!CAN_PSR(dev_priv))
> @@ -745,7 +745,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
>
> dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
> dev_priv->psr.busy_frontbuffer_bits = 0;
> - dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
> + dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
>
> /*
> @@ -988,7 +988,7 @@ void intel_psr_update(struct intel_dp *intel_dp,
> int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
> u32 *out_value)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 47f5d87a938a..1047357c15c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -1087,7 +1087,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
> {
> struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> int ret;
>
> if (!crtc_state->has_hdmi_sink)
> @@ -1276,8 +1276,8 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
> to_intel_sdvo_connector_state(conn_state);
> struct intel_sdvo_connector *intel_sdvo_connector =
> to_intel_sdvo_connector(conn_state->connector);
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> - struct drm_display_mode *mode = &pipe_config->base.mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> + struct drm_display_mode *mode = &pipe_config->hw.mode;
>
> DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
> pipe_config->pipe_bpp = 8*3;
> @@ -1429,13 +1429,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> const struct intel_sdvo_connector_state *sdvo_state =
> to_intel_sdvo_connector_state(conn_state);
> const struct intel_sdvo_connector *intel_sdvo_connector =
> to_intel_sdvo_connector(conn_state->connector);
> - const struct drm_display_mode *mode = &crtc_state->base.mode;
> + const struct drm_display_mode *mode = &crtc_state->hw.mode;
> struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
> u32 sdvox;
> struct intel_sdvo_in_out_map in_out;
> @@ -1629,7 +1629,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
> flags |= DRM_MODE_FLAG_NVSYNC;
> }
>
> - pipe_config->base.adjusted_mode.flags |= flags;
> + pipe_config->hw.adjusted_mode.flags |= flags;
>
> /*
> * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
> @@ -1649,7 +1649,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
> if (pipe_config->pixel_multiplier)
> dotclock /= pipe_config->pixel_multiplier;
>
> - pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> + pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
>
> /* Cross check the port pixel multiplier with the sdvo encoder state. */
> if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
> @@ -1701,7 +1701,7 @@ static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
> const struct drm_connector_state *conn_state)
> {
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> struct drm_connector *connector = conn_state->connector;
> u8 *eld = connector->eld;
>
> @@ -1723,7 +1723,7 @@ static void intel_disable_sdvo(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> u32 temp;
>
> if (old_crtc_state->has_audio)
> @@ -1785,7 +1785,7 @@ static void intel_enable_sdvo(struct intel_encoder *encoder,
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> u32 temp;
> bool input1, input2;
> int i;
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 633fa8069348..526a9366b682 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -81,9 +81,9 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> */
> void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
> long timeout = msecs_to_jiffies_timeout(1);
> int scanline, min, max, vblank_start;
> wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
> @@ -190,7 +190,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
> */
> void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
> int scanline_end = intel_get_crtc_scanline(crtc);
> u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
> @@ -203,14 +203,15 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> * Would be slightly nice to just grab the vblank count and arm the
> * event outside of the critical section - the spinlock might spin for a
> * while ... */
> - if (new_crtc_state->base.event) {
> + if (new_crtc_state->uapi.event) {
> WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
>
> spin_lock(&crtc->base.dev->event_lock);
> - drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
> + drm_crtc_arm_vblank_event(&crtc->base,
> + new_crtc_state->uapi.event);
> spin_unlock(&crtc->base.dev->event_lock);
>
> - new_crtc_state->base.event = NULL;
> + new_crtc_state->uapi.event = NULL;
> }
>
> local_irq_enable();
> @@ -1515,7 +1516,7 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
> const struct drm_rect *dst = &plane_state->base.dst;
> int src_x, src_w, src_h, crtc_w, crtc_h;
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> unsigned int stride = plane_state->color_plane[0].stride;
> unsigned int cpp = fb->format->cpp[0];
> unsigned int width_bytes;
> @@ -1588,7 +1589,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
> }
>
> ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> - &crtc_state->base,
> + &crtc_state->uapi,
> min_scale, max_scale,
> true, true);
> if (ret)
> @@ -1645,7 +1646,7 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> return ret;
>
> ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> - &crtc_state->base,
> + &crtc_state->uapi,
> DRM_PLANE_HELPER_NO_SCALING,
> DRM_PLANE_HELPER_NO_SCALING,
> true, true);
> @@ -1729,8 +1730,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> }
>
> /* Y-tiling is not supported in IF-ID Interlace mode */
> - if (crtc_state->base.enable &&
> - crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
> + if (crtc_state->hw.enable &&
> + crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
> (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
> fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> @@ -1810,7 +1811,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> }
>
> ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> - &crtc_state->base,
> + &crtc_state->uapi,
> min_scale, max_scale,
> true, true);
> if (ret)
> diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
> index 70726b481244..4499d402c316 100644
> --- a/drivers/gpu/drm/i915/display/intel_tv.c
> +++ b/drivers/gpu/drm/i915/display/intel_tv.c
> @@ -924,7 +924,7 @@ intel_enable_tv(struct intel_encoder *encoder,
>
> /* Prevents vblank waits from timing out in intel_tv_detect_type() */
> intel_wait_for_vblank(dev_priv,
> - to_intel_crtc(pipe_config->base.crtc)->pipe);
> + to_intel_crtc(pipe_config->uapi.crtc)->pipe);
>
> I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
> }
> @@ -1085,7 +1085,7 @@ intel_tv_get_config(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
> struct drm_display_mode mode = {};
> u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
> struct tv_mode tv_mode = {};
> @@ -1188,7 +1188,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
> to_intel_tv_connector_state(conn_state);
> const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
> int hdisplay = adjusted_mode->crtc_hdisplay;
> int vdisplay = adjusted_mode->crtc_vdisplay;
>
> @@ -1417,7 +1417,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_tv *intel_tv = enc_to_tv(encoder);
> const struct intel_tv_connector_state *tv_conn_state =
> to_intel_tv_connector_state(conn_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index d4fb7f16f9f6..38c181499505 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -329,8 +329,8 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> int column_index = 0;
> u8 line_buf_depth = 0;
>
> - vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
> - vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
> + vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> + vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
> vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> pipe_config->dsc_params.slice_count);
> /*
> @@ -459,7 +459,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> enum intel_display_power_domain
> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> /*
> @@ -483,7 +483,7 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
> enum pipe pipe = crtc->pipe;
> @@ -902,7 +902,7 @@ static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
> void intel_dsc_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum pipe pipe = crtc->pipe;
> i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> @@ -938,7 +938,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
>
> void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 50064cde0724..16f93d1e71e5 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -261,9 +261,9 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
> struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
> base);
> struct intel_connector *intel_connector = intel_dsi->attached_connector;
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> - struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> int ret;
>
> DRM_DEBUG_KMS("\n");
> @@ -624,7 +624,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
>
> @@ -746,7 +746,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
> const struct drm_connector_state *conn_state)
> {
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> - struct drm_crtc *crtc = pipe_config->base.crtc;
> + struct drm_crtc *crtc = pipe_config->uapi.crtc;
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum pipe pipe = intel_crtc->pipe;
> @@ -1032,9 +1032,9 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_display_mode *adjusted_mode =
> - &pipe_config->base.adjusted_mode;
> + &pipe_config->hw.adjusted_mode;
> struct drm_display_mode *adjusted_mode_sw;
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> unsigned int lane_count = intel_dsi->lane_count;
> unsigned int bpp, fmt;
> @@ -1045,7 +1045,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
> crtc_hblank_start_sw, crtc_hblank_end_sw;
>
> /* FIXME: hw readout should not depend on SW state */
> - adjusted_mode_sw = &crtc->config->base.adjusted_mode;
> + adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
>
> /*
> * Atleast one port is active as encoder->get_config called only if
> @@ -1204,7 +1204,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
> }
>
> if (pclk) {
> - pipe_config->base.adjusted_mode.crtc_clock = pclk;
> + pipe_config->hw.adjusted_mode.crtc_clock = pclk;
> pipe_config->port_clock = pclk;
> }
> }
> @@ -1315,9 +1315,9 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> struct drm_encoder *encoder = &intel_encoder->base;
> struct drm_device *dev = encoder->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> - const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> enum port port;
> unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> u32 val, tmp;
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index fec9fb7cc384..7ce3ae1ec586 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2752,11 +2752,11 @@ static int i915_display_info(struct seq_file *m, void *unused)
>
> seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
> crtc->base.base.id, pipe_name(crtc->pipe),
> - yesno(pipe_config->base.active),
> + yesno(pipe_config->hw.active),
> pipe_config->pipe_src_w, pipe_config->pipe_src_h,
> yesno(pipe_config->dither), pipe_config->pipe_bpp);
>
> - if (pipe_config->base.active) {
> + if (pipe_config->hw.active) {
> struct intel_plane *cursor =
> to_intel_plane(crtc->base.cursor);
>
> @@ -4208,11 +4208,11 @@ static int i915_drrs_ctl_set(void *data, u64 val)
>
> crtc_state = to_intel_crtc_state(crtc->base.state);
>
> - if (!crtc_state->base.active ||
> + if (!crtc_state->hw.active ||
> !crtc_state->has_drrs)
> goto out;
>
> - commit = crtc_state->base.commit;
> + commit = crtc_state->uapi.commit;
> if (commit) {
> ret = wait_for_completion_interruptible(&commit->hw_done);
> if (ret)
> @@ -4224,7 +4224,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
> struct intel_encoder *encoder;
> struct intel_dp *intel_dp;
>
> - if (!(crtc_state->base.connector_mask &
> + if (!(crtc_state->uapi.connector_mask &
> drm_connector_mask(connector)))
> continue;
>
> @@ -4283,14 +4283,14 @@ i915_fifo_underrun_reset_write(struct file *filp,
> return ret;
>
> crtc_state = to_intel_crtc_state(intel_crtc->base.state);
> - commit = crtc_state->base.commit;
> + commit = crtc_state->uapi.commit;
> if (commit) {
> ret = wait_for_completion_interruptible(&commit->hw_done);
> if (!ret)
> ret = wait_for_completion_interruptible(&commit->flip_done);
> }
>
> - if (!ret && crtc_state->base.active) {
> + if (!ret && crtc_state->hw.active) {
> DRM_DEBUG_KMS("Re-arming FIFO underruns on pipe %c\n",
> pipe_name(intel_crtc->pipe));
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5e6e54cb22fe..4c9359981c24 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -464,7 +464,7 @@ static const int pessimal_latency_ns = 5000;
>
> static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
> enum pipe pipe = crtc->pipe;
> @@ -798,7 +798,7 @@ static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
> struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>
> /* FIXME check the 'enable' instead */
> - if (!crtc_state->base.active)
> + if (!crtc_state->hw.active)
> return false;
>
> /*
> @@ -851,7 +851,7 @@ static void pineview_update_wm(struct intel_crtc *unused_crtc)
> crtc = single_enabled_crtc(dev_priv);
> if (crtc) {
> const struct drm_display_mode *adjusted_mode =
> - &crtc->config->base.adjusted_mode;
> + &crtc->config->hw.adjusted_mode;
> const struct drm_framebuffer *fb =
> crtc->base.primary->state->fb;
> int cpp = fb->format->cpp[0];
> @@ -1087,7 +1087,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
> unsigned int clock, htotal, cpp, width, wm;
>
> @@ -1144,7 +1144,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
> static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
> int level, enum plane_id plane_id, u16 value)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> bool dirty = false;
>
> for (; level < intel_wm_num_levels(dev_priv); level++) {
> @@ -1160,7 +1160,7 @@ static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
> static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
> int level, u16 value)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> bool dirty = false;
>
> /* NORMAL level doesn't have an FBC watermark */
> @@ -1262,7 +1262,7 @@ static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
> static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
> int level)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> if (level > dev_priv->wm.max_level)
> return false;
> @@ -1300,9 +1300,9 @@ static void g4x_invalidate_wms(struct intel_crtc *crtc,
>
> static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_atomic_state *state =
> - to_intel_atomic_state(crtc_state->base.state);
> + to_intel_atomic_state(crtc_state->uapi.state);
> struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
> int num_active_planes = hweight8(crtc_state->active_planes &
> ~BIT(PLANE_CURSOR));
> @@ -1389,17 +1389,17 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
>
> static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
> const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
> struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(new_crtc_state->base.state);
> + to_intel_atomic_state(new_crtc_state->uapi.state);
> const struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(intel_state, crtc);
> const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
> enum plane_id plane_id;
>
> - if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
> + if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
> *intermediate = *optimal;
>
> intermediate->cxsr = false;
> @@ -1531,8 +1531,8 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
> static void g4x_initial_watermarks(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> mutex_lock(&dev_priv->wm.wm_mutex);
> crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
> @@ -1543,8 +1543,8 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
> static void g4x_optimize_watermarks(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> if (!crtc_state->wm.need_postvbl_update)
> return;
> @@ -1593,7 +1593,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
> struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> unsigned int clock, htotal, cpp, width, wm;
>
> if (dev_priv->wm.pri_latency[level] == 0)
> @@ -1631,7 +1631,7 @@ static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
>
> static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> const struct g4x_pipe_wm *raw =
> &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
> struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
> @@ -1743,7 +1743,7 @@ static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
> static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
> int level, enum plane_id plane_id, u16 value)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int num_levels = intel_wm_num_levels(dev_priv);
> bool dirty = false;
>
> @@ -1818,16 +1818,16 @@ static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
>
> static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_atomic_state *state =
> - to_intel_atomic_state(crtc_state->base.state);
> + to_intel_atomic_state(crtc_state->uapi.state);
> struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
> const struct vlv_fifo_state *fifo_state =
> &crtc_state->wm.vlv.fifo_state;
> int num_active_planes = hweight8(crtc_state->active_planes &
> ~BIT(PLANE_CURSOR));
> - bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
> + bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
> const struct intel_plane_state *old_plane_state;
> const struct intel_plane_state *new_plane_state;
> struct intel_plane *plane;
> @@ -1926,7 +1926,7 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_uncore *uncore = &dev_priv->uncore;
> const struct vlv_fifo_state *fifo_state =
> @@ -2022,17 +2022,17 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>
> static int vlv_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
> const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
> struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(new_crtc_state->base.state);
> + to_intel_atomic_state(new_crtc_state->uapi.state);
> const struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(intel_state, crtc);
> const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
> int level;
>
> - if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
> + if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
> *intermediate = *optimal;
>
> intermediate->cxsr = false;
> @@ -2150,8 +2150,8 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
> static void vlv_initial_watermarks(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> mutex_lock(&dev_priv->wm.wm_mutex);
> crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
> @@ -2162,8 +2162,8 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
> static void vlv_optimize_watermarks(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> if (!crtc_state->wm.need_postvbl_update)
> return;
> @@ -2188,7 +2188,7 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
> /* self-refresh has much higher latency */
> static const int sr_latency_ns = 12000;
> const struct drm_display_mode *adjusted_mode =
> - &crtc->config->base.adjusted_mode;
> + &crtc->config->hw.adjusted_mode;
> const struct drm_framebuffer *fb =
> crtc->base.primary->state->fb;
> int clock = adjusted_mode->crtc_clock;
> @@ -2269,7 +2269,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *adjusted_mode =
> - &crtc->config->base.adjusted_mode;
> + &crtc->config->hw.adjusted_mode;
> const struct drm_framebuffer *fb =
> crtc->base.primary->state->fb;
> int cpp;
> @@ -2296,7 +2296,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *adjusted_mode =
> - &crtc->config->base.adjusted_mode;
> + &crtc->config->hw.adjusted_mode;
> const struct drm_framebuffer *fb =
> crtc->base.primary->state->fb;
> int cpp;
> @@ -2344,7 +2344,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> /* self-refresh has much higher latency */
> static const int sr_latency_ns = 6000;
> const struct drm_display_mode *adjusted_mode =
> - &enabled->config->base.adjusted_mode;
> + &enabled->config->hw.adjusted_mode;
> const struct drm_framebuffer *fb =
> enabled->base.primary->state->fb;
> int clock = adjusted_mode->crtc_clock;
> @@ -2402,7 +2402,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
> if (crtc == NULL)
> return;
>
> - adjusted_mode = &crtc->config->base.adjusted_mode;
> + adjusted_mode = &crtc->config->hw.adjusted_mode;
> planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
> &i845_wm_info,
> dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
> @@ -2492,7 +2492,7 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
> return method1;
>
> method2 = ilk_wm_method2(crtc_state->pixel_rate,
> - crtc_state->base.adjusted_mode.crtc_htotal,
> + crtc_state->hw.adjusted_mode.crtc_htotal,
> drm_rect_width(&plane_state->base.dst),
> cpp, mem_value);
>
> @@ -2520,7 +2520,7 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
>
> method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
> method2 = ilk_wm_method2(crtc_state->pixel_rate,
> - crtc_state->base.adjusted_mode.crtc_htotal,
> + crtc_state->hw.adjusted_mode.crtc_htotal,
> drm_rect_width(&plane_state->base.dst),
> cpp, mem_value);
> return min(method1, method2);
> @@ -2545,7 +2545,7 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
> cpp = plane_state->base.fb->format->cpp[0];
>
> return ilk_wm_method2(crtc_state->pixel_rate,
> - crtc_state->base.adjusted_mode.crtc_htotal,
> + crtc_state->hw.adjusted_mode.crtc_htotal,
> drm_rect_width(&plane_state->base.dst),
> cpp, mem_value);
> }
> @@ -2767,12 +2767,12 @@ static u32
> hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
> {
> const struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(crtc_state->base.state);
> + to_intel_atomic_state(crtc_state->uapi.state);
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> u32 linetime, ips_linetime;
>
> - if (!crtc_state->base.active)
> + if (!crtc_state->hw.active)
> return 0;
> if (WARN_ON(adjusted_mode->crtc_clock == 0))
> return 0;
> @@ -3082,11 +3082,9 @@ static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
> /* Compute new watermarks for the pipe */
> static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> {
> - struct drm_atomic_state *state = crtc_state->base.state;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct intel_pipe_wm *pipe_wm;
> - struct drm_device *dev = state->dev;
> - const struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_plane *plane;
> const struct intel_plane_state *plane_state;
> const struct intel_plane_state *pristate = NULL;
> @@ -3106,7 +3104,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> curstate = plane_state;
> }
>
> - pipe_wm->pipe_enabled = crtc_state->base.active;
> + pipe_wm->pipe_enabled = crtc_state->hw.active;
> if (sprstate) {
> pipe_wm->sprites_enabled = sprstate->base.visible;
> pipe_wm->sprites_scaled = sprstate->base.visible &&
> @@ -3163,11 +3161,11 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> */
> static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
> {
> - struct intel_crtc *intel_crtc = to_intel_crtc(newstate->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(newstate->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
> struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(newstate->base.state);
> + to_intel_atomic_state(newstate->uapi.state);
> const struct intel_crtc_state *oldstate =
> intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
> const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
> @@ -3179,7 +3177,7 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
> * and after the vblank.
> */
> *a = newstate->wm.ilk.optimal;
> - if (!newstate->base.active || drm_atomic_crtc_needs_modeset(&newstate->base) ||
> + if (!newstate->hw.active || drm_atomic_crtc_needs_modeset(&newstate->uapi) ||
> intel_state->skip_intermediate_wm)
> return 0;
>
> @@ -3756,7 +3754,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> crtc_state = to_intel_crtc_state(crtc->base.state);
>
> - if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> return false;
>
> for_each_intel_plane_on_crtc(dev, crtc, plane) {
> @@ -3806,7 +3804,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
> if (INTEL_GEN(dev_priv) < 11)
> return ddb_size - 4; /* 4 blocks for bypass path allocation */
>
> - adjusted_mode = &crtc_state->base.adjusted_mode;
> + adjusted_mode = &crtc_state->hw.adjusted_mode;
> total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
>
> /*
> @@ -3835,16 +3833,16 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> struct skl_ddb_entry *alloc, /* out */
> int *num_active /* out */)
> {
> - struct drm_atomic_state *state = crtc_state->base.state;
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> - struct drm_crtc *for_crtc = crtc_state->base.crtc;
> + struct drm_crtc *for_crtc = crtc_state->uapi.crtc;
> const struct intel_crtc *crtc;
> u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
> enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
> u16 ddb_size;
> u32 i;
>
> - if (WARN_ON(!state) || !crtc_state->base.active) {
> + if (WARN_ON(!state) || !crtc_state->hw.active) {
> alloc->start = 0;
> alloc->end = 0;
> *num_active = hweight8(dev_priv->active_pipes);
> @@ -3883,11 +3881,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> */
> for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> + &crtc_state->hw.adjusted_mode;
> enum pipe pipe = crtc->pipe;
> int hdisplay, vdisplay;
>
> - if (!crtc_state->base.enable)
> + if (!crtc_state->hw.enable)
> continue;
>
> drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
> @@ -3918,7 +3916,7 @@ static unsigned int
> skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> int num_active)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int level, max_level = ilk_wm_max_level(dev_priv);
> struct skl_wm_level wm = {};
> int ret, min_ddb_alloc = 0;
> @@ -4076,7 +4074,7 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
> {
> uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
>
> - if (!crtc_state->base.enable)
> + if (!crtc_state->hw.enable)
> return pipe_downscale;
>
> if (crtc_state->pch_pfit.enabled) {
> @@ -4108,7 +4106,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> - struct drm_atomic_state *state = crtc_state->base.state;
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> const struct intel_plane_state *plane_state;
> struct intel_plane *plane;
> int crtc_clock, dotclk;
> @@ -4116,7 +4114,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> uint_fixed_16_16_t pipe_downscale;
> uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
>
> - if (!crtc_state->base.enable)
> + if (!crtc_state->hw.enable)
> return 0;
>
> intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> @@ -4142,7 +4140,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>
> pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
>
> - crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
> + crtc_clock = crtc_state->hw.adjusted_mode.crtc_clock;
> dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
>
> if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> @@ -4209,7 +4207,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> u64 *plane_data_rate,
> u64 *uv_plane_data_rate)
> {
> - struct drm_atomic_state *state = crtc_state->base.state;
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> struct intel_plane *plane;
> const struct intel_plane_state *plane_state;
> u64 total_data_rate = 0;
> @@ -4244,7 +4242,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state;
> u64 total_data_rate = 0;
>
> - if (WARN_ON(!crtc_state->base.state))
> + if (WARN_ON(!crtc_state->uapi.state))
> return 0;
>
> /* Calculate and cache data rate for each plane */
> @@ -4288,8 +4286,8 @@ static int
> skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> struct skl_ddb_allocation *ddb /* out */)
> {
> - struct drm_atomic_state *state = crtc_state->base.state;
> - struct drm_crtc *crtc = crtc_state->base.crtc;
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> + struct drm_crtc *crtc = crtc_state->uapi.crtc;
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> @@ -4311,7 +4309,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> if (WARN_ON(!state))
> return 0;
>
> - if (!crtc_state->base.active) {
> + if (!crtc_state->hw.active) {
> alloc->start = alloc->end = 0;
> return 0;
> }
> @@ -4553,7 +4551,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
> u32 crtc_htotal;
> uint_fixed_16_16_t linetime_us;
>
> - if (!crtc_state->base.active)
> + if (!crtc_state->hw.active)
> return u32_to_fixed16(0);
>
> pixel_rate = crtc_state->pixel_rate;
> @@ -4561,7 +4559,7 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
> if (WARN_ON(pixel_rate == 0))
> return u32_to_fixed16(0);
>
> - crtc_htotal = crtc_state->base.adjusted_mode.crtc_htotal;
> + crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
> linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
>
> return linetime_us;
> @@ -4596,7 +4594,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> u32 plane_pixel_rate, struct skl_wm_params *wp,
> int color_plane)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> u32 interm_pbpl;
>
> @@ -4717,7 +4715,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> const struct skl_wm_level *result_prev,
> struct skl_wm_level *result /* out */)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> u32 latency = dev_priv->wm.skl_latency[level];
> uint_fixed_16_16_t method1, method2;
> uint_fixed_16_16_t selected_result;
> @@ -4743,14 +4741,14 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
> wp->cpp, latency, wp->dbuf_block_size);
> method2 = skl_wm_method2(wp->plane_pixel_rate,
> - crtc_state->base.adjusted_mode.crtc_htotal,
> + crtc_state->hw.adjusted_mode.crtc_htotal,
> latency,
> wp->plane_blocks_per_line);
>
> if (wp->y_tiled) {
> selected_result = max_fixed16(method2, wp->y_tile_minimum);
> } else {
> - if ((wp->cpp * crtc_state->base.adjusted_mode.crtc_htotal /
> + if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
> wp->dbuf_block_size < 1) &&
> (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
> selected_result = method2;
> @@ -4841,7 +4839,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> const struct skl_wm_params *wm_params,
> struct skl_wm_level *levels)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int level, max_level = ilk_wm_max_level(dev_priv);
> struct skl_wm_level *result_prev = &levels[0];
>
> @@ -4858,7 +4856,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> static u32
> skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_atomic_state *state = crtc_state->base.state;
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> struct drm_i915_private *dev_priv = to_i915(state->dev);
> uint_fixed_16_16_t linetime_us;
> u32 linetime_wm;
> @@ -4877,7 +4875,7 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> const struct skl_wm_params *wp,
> struct skl_plane_wm *wm)
> {
> - struct drm_device *dev = crtc_state->base.crtc->dev;
> + struct drm_device *dev = crtc_state->uapi.crtc->dev;
> const struct drm_i915_private *dev_priv = to_i915(dev);
> u16 trans_min, trans_y_tile_min;
> const u16 trans_amount = 10; /* This is configurable amount */
> @@ -5037,7 +5035,7 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
>
> static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> struct intel_plane *plane;
> const struct intel_plane_state *plane_state;
> @@ -5227,8 +5225,8 @@ static int
> skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
> struct intel_crtc_state *new_crtc_state)
> {
> - struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->base.state);
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
> + struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->uapi.state);
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_plane *plane;
>
> @@ -5529,7 +5527,7 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
> * power well the hardware state will go out of sync
> * with the software state.
> */
> - if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) &&
> + if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi) &&
> skl_plane_wm_equals(dev_priv,
> &old_crtc_state->wm.skl.optimal.planes[plane_id],
> &new_crtc_state->wm.skl.optimal.planes[plane_id]))
> @@ -5597,7 +5595,7 @@ skl_compute_wm(struct intel_atomic_state *state)
> static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> enum pipe pipe = crtc->pipe;
> @@ -5611,7 +5609,7 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
> static void skl_initial_wm(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_device *dev = intel_crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct skl_ddb_values *results = &state->wm_results;
> @@ -5621,7 +5619,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
>
> mutex_lock(&dev_priv->wm.wm_mutex);
>
> - if (crtc_state->base.active_changed)
> + if (crtc_state->uapi.active_changed)
> skl_atomic_update_crtc_wm(state, crtc_state);
>
> mutex_unlock(&dev_priv->wm.wm_mutex);
> @@ -5680,8 +5678,8 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
> static void ilk_initial_watermarks(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> mutex_lock(&dev_priv->wm.wm_mutex);
> crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
> @@ -5692,8 +5690,8 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
> static void ilk_optimize_watermarks(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> if (!crtc_state->wm.need_postvbl_update)
> return;
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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