[Intel-gfx] [PATCH 2/3] drm/i915/tgl: Add HDC Pipeline Flush
Chris Wilson
chris at chris-wilson.co.uk
Fri Oct 11 18:13:53 UTC 2019
Quoting Mika Kuoppala (2019-10-11 14:39:10)
> Add hdc pipeline flush to ensure memory state is coherent
> in L3 when we are done.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
> drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 8c8e6bf824a9..696b6495b0da 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -232,6 +232,7 @@
> #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
> #define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE (1<<10) /* gen12 */
> #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
> +#define PIPE_CONTROL_HDC_PIPELINE_FLUSH (1<<9) /* gen 12 */
> #define PIPE_CONTROL_NOTIFY (1<<8)
> #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
> #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index c6fbc723566f..967e5b2e5e80 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3188,6 +3188,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> + flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
Adding a flush here has no effect, see gen12_fini_breadcrumbs_rcs.
>
> flags |= PIPE_CONTROL_QW_WRITE;
> --
> 2.17.1
>
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