[Intel-gfx] [PATCH 1/3] drm/i915/tgl: Include ro parts of l3 to invalidate
Chris Wilson
chris at chris-wilson.co.uk
Fri Oct 11 18:15:06 UTC 2019
Quoting Mika Kuoppala (2019-10-11 14:39:09)
> Aim for completeness and invalidate also the ro parts
> in l3 cache. This might allow to get rid of the preparser
> disable/enable workaround on invalidation path.
>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
> drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index b0227ab2fe1b..8c8e6bf824a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -230,6 +230,7 @@
> #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
> #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on ILK */
> #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
> +#define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE (1<<10) /* gen12 */
Ack.
> #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
> #define PIPE_CONTROL_NOTIFY (1<<8)
> #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index b00499cc7586..c6fbc723566f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3213,6 +3213,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
> flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
> flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
> flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
> + flags |= PIPE_CONTROL_L3_RO_CACHE_INVALIDATE;
>
> flags |= PIPE_CONTROL_STORE_DATA_INDEX;
> flags |= PIPE_CONTROL_QW_WRITE;
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris
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