[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev4)

[Patchwork]

== Series Details ==

Series: Clear Color Support for TGL Render Decompression (rev4)
URL   : https://patchwork.freedesktop.org/series/66814/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5b2a67fc7d74 drm/framebuffer: Format modifier for Intel Gen-12 render compression
7ae892f52e6b drm/i915: Use intel_tile_height() instead of re-implementing
6e151153d384 drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
fe009ce2a753 drm/i915/tgl: Gen-12 render decompression
922c0f17cfcb drm/i915: Extract framebufer CCS offset checks into a function
3e0c8644766c drm/framebuffer: Format modifier for Intel Gen-12 media compression
e81ef5974cd9 drm/fb: Extend format_info member arrays to handle four planes
6af18a7bd390 Gen-12 display can decompress surfaces compressed by the media engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13: 
compressed buffers. Unlike render decompression, plane 6 and  plane 7 do not

-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/display/intel_display.c:2699:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct drm_framebuffer *fb, int color_plane)

-:120: WARNING:LONG_LINE: line over 100 characters
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:2706:
+		} mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2, 16}, .vsub = {1, 32, 2, 32} };

total: 0 errors, 3 warnings, 0 checks, 509 lines checked
0a4f1ab7678c drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
-:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#7: 
Gen12 display can decompress surfaces compressed by render engine with Clear Color, add

-:33: ERROR:TRAILING_WHITESPACE: trailing whitespace
#33: FILE: include/uapi/drm/drm_fourcc.h:442:
+ * be ignored. The size of clear color should be 64 bits. A CCS_CC cache line $

-:34: ERROR:TRAILING_WHITESPACE: trailing whitespace
#34: FILE: include/uapi/drm/drm_fourcc.h:443:
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface $

total: 2 errors, 1 warnings, 0 checks, 17 lines checked
cb25ebee96c9 drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
-:252: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#252: FILE: drivers/gpu/drm/i915/i915_reg.h:6791:
+#define PLANE_CC_VAL(pipe, plane)	\
+	_MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))

total: 0 errors, 0 warnings, 1 checks, 198 lines checked